| /drivers/gpu/drm/panel/ |
| D | panel-simple.c | 854 .htotal = 1280 + 40 + 80 + 40,
880 .htotal = 480 + 2 + 41 + 2,
904 .htotal = 800 + 0 + 255 + 0,
954 .htotal = 1024 + 156 + 8 + 156,
1001 .htotal = 1366 + 20 + 70,
1024 .htotal = 1366 + 48 + 32 + 10,
1052 .htotal = 1366 + 40 + 40 + 32,
1081 .htotal = 1366 + 48 + 32 + 20,
1103 .htotal = 1920 + 58 + 42 + 60,
1133 .htotal = 1920 + 172 + 80 + 60,
[all …]
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| D | panel-arm-versatile.c | 141 .htotal = 320 + 6 + 6 + 6,
164 .htotal = 640 + 24 + 96 + 24,
186 .htotal = 176 + 2 + 3 + 3,
209 .htotal = 240 + 10 + 10 + 20,
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| D | panel-tpo-tpg110.c | 109 .htotal = 800 + 40 + 1 + 216,
125 .htotal = 640 + 24 + 1 + 136,
141 .htotal = 480 + 2 + 1 + 43,
157 .htotal = 480 + 2 + 1 + 43,
173 .htotal = 400 + 20 + 1 + 108,
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| /drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4_dsi_encoder.c | 61 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dsi_encoder_mode_set()
62 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dsi_encoder_mode_set()
64 vsync_period = mode->vtotal * mode->htotal; in mdp4_dsi_encoder_mode_set()
65 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dsi_encoder_mode_set()
66 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dsi_hsync_skew; in mdp4_dsi_encoder_mode_set()
67 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dsi_hsync_s… in mdp4_dsi_encoder_mode_set()
71 MDP4_DSI_HSYNC_CTRL_PERIOD(mode->htotal)); in mdp4_dsi_encoder_mode_set()
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| D | mdp4_dtv_encoder.c | 66 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dtv_encoder_mode_set()
67 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dtv_encoder_mode_set()
69 vsync_period = mode->vtotal * mode->htotal; in mdp4_dtv_encoder_mode_set()
70 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dtv_encoder_mode_set()
71 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp4_dtv_encoder_mode_set()
72 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp4_dtv_encoder_mode_set()
76 MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal)); in mdp4_dtv_encoder_mode_set()
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| D | mdp4_lcdc_encoder.c | 241 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_lcdc_encoder_mode_set()
242 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_lcdc_encoder_mode_set()
244 vsync_period = mode->vtotal * mode->htotal; in mdp4_lcdc_encoder_mode_set()
245 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_lcdc_encoder_mode_set()
246 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + lcdc_hsync_skew; in mdp4_lcdc_encoder_mode_set()
247 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_… in mdp4_lcdc_encoder_mode_set()
251 MDP4_LCDC_HSYNC_CTRL_PERIOD(mode->htotal)); in mdp4_lcdc_encoder_mode_set()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_tv.c | 315 u16 hblank_start, hblank_end, htotal; member
389 .hblank_start = 836, .htotal = 857,
431 .hblank_start = 836, .htotal = 857,
474 .hblank_start = 836, .htotal = 857,
517 .hblank_start = 836, .htotal = 857,
560 .hblank_start = 844, .htotal = 863,
605 .hblank_start = 844, .htotal = 863,
647 .hblank_start = 842, .htotal = 857,
671 .hblank_start = 859, .htotal = 863,
695 .hblank_start = 1580, .htotal = 1649,
[all …]
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| /drivers/media/i2c/ |
| D | ths8200.c | 61 static inline unsigned htotal(const struct v4l2_bt_timings *t) in htotal() function
252 ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff); in ths8200_setup()
254 ((htotal(bt)/2) >> 8) & 0x0f); in ths8200_setup()
257 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8); in ths8200_setup()
258 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff); in ths8200_setup()
308 (htotal(bt) >> 8) & 0x1f); in ths8200_setup()
309 ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); in ths8200_setup()
356 "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt), in ths8200_setup()
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| /drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_encoder.c | 84 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp5_vid_encoder_mode_set()
85 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp5_vid_encoder_mode_set()
87 vsync_period = mode->vtotal * mode->htotal; in mdp5_vid_encoder_mode_set()
88 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp5_vid_encoder_mode_set()
89 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp5_vid_encoder_mode_set()
90 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp5_vid_encoder_mode_set()
98 display_v_start += mode->htotal - mode->hsync_start; in mdp5_vid_encoder_mode_set()
106 MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal)); in mdp5_vid_encoder_mode_set()
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| /drivers/video/fbdev/core/ |
| D | fbmon.c | 722 int vtotal, htotal; in fb_get_monitor_limits() local
734 htotal = mode->xres + mode->right_margin + mode->hsync_len in fb_get_monitor_limits()
745 hscan = (pixclock + htotal / 2) / htotal; in fb_get_monitor_limits()
1024 u32 htotal; member
1155 timings->htotal = timings->hactive + timings->hblank; in fb_timings_vfreq()
1156 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1166 timings->htotal = timings->hactive + timings->hblank; in fb_timings_hfreq()
1167 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
1174 timings->htotal = timings->hactive + timings->hblank; in fb_timings_dclk()
1175 timings->hfreq = timings->dclk/timings->htotal; in fb_timings_dclk()
[all …]
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| D | fbcvt.c | 44 u32 htotal; member
132 hsync = (FB_CVT_CELLSIZE * cvt->htotal)/100; in fb_cvt_hsync()
177 pixclock = (cvt->f_refresh * cvt->vtotal * cvt->htotal)/1000; in fb_cvt_pixclock()
179 pixclock = (cvt->htotal * 1000000)/cvt->hperiod; in fb_cvt_pixclock()
354 cvt.htotal = cvt.active_pixels + cvt.hblank; in fb_find_mode_cvt()
357 cvt.hfreq = cvt.pixclock/cvt.htotal; in fb_find_mode_cvt()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20v2.c | 806 unsigned int htotal = dst->htotal; in dml20v2_rq_dlg_get_dlg_params() local
931 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal in dml20v2_rq_dlg_get_dlg_params()
942 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml20v2_rq_dlg_get_dlg_params()
993 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml20v2_rq_dlg_get_dlg_params()
1040 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml20v2_rq_dlg_get_dlg_params()
1047 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml20v2_rq_dlg_get_dlg_params()
1078 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); in dml20v2_rq_dlg_get_dlg_params()
1117 if (htotal <= 75) { in dml20v2_rq_dlg_get_dlg_params()
1411 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml20v2_rq_dlg_get_dlg_params()
1417 * (double) htotal * ref_freq_to_pix_freq in dml20v2_rq_dlg_get_dlg_params()
[all …]
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| D | display_rq_dlg_calc_20.c | 806 unsigned int htotal = dst->htotal; in dml20_rq_dlg_get_dlg_params() local
931 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal in dml20_rq_dlg_get_dlg_params()
942 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml20_rq_dlg_get_dlg_params()
992 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml20_rq_dlg_get_dlg_params()
1039 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml20_rq_dlg_get_dlg_params()
1046 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml20_rq_dlg_get_dlg_params()
1077 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); in dml20_rq_dlg_get_dlg_params()
1116 if (htotal <= 75) { in dml20_rq_dlg_get_dlg_params()
1410 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml20_rq_dlg_get_dlg_params()
1416 * (double) htotal * ref_freq_to_pix_freq in dml20_rq_dlg_get_dlg_params()
[all …]
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calc_auto.c | 176 …eil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_cloc… in mode_support_and_system_configuration()
194 v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0; in mode_support_and_system_configuration()
197 v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5; in mode_support_and_system_configuration()
242 …&& v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_cloc… in mode_support_and_system_configuration()
245 …else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel… in mode_support_and_system_configuration()
559 …v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / … in mode_support_and_system_configuration()
562 …htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yp… in mode_support_and_system_configuration()
785 v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); in mode_support_and_system_configuration()
802 …htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k… in mode_support_and_system_configuration()
804 …->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_cloc… in mode_support_and_system_configuration()
[all …]
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| /drivers/gpu/drm/mgag200/ |
| D | mgag200_mode.c | 356 unsigned int hdisplay, hsyncstart, hsyncend, htotal; in mgag200_set_mode_regs() local
363 htotal = mode->htotal / 8 - 1; in mgag200_set_mode_regs()
366 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) in mgag200_set_mode_regs()
367 htotal++; in mgag200_set_mode_regs()
386 crtcext1 = (((htotal - 4) & 0x100) >> 8) | in mgag200_set_mode_regs()
389 (htotal & 0x40); in mgag200_set_mode_regs()
401 WREG_CRT(0, htotal - 4); in mgag200_set_mode_regs()
404 WREG_CRT(3, (htotal & 0x1F) | 0x80); in mgag200_set_mode_regs()
406 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); in mgag200_set_mode_regs()
692 if (!mode->htotal || !mode->vtotal || !mode->clock) in mga_vga_calculate_mode_bandwidth()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 852 unsigned int htotal = dst->htotal; in dml_rq_dlg_get_dlg_params() local
977 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal in dml_rq_dlg_get_dlg_params()
988 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml_rq_dlg_get_dlg_params()
1044 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml_rq_dlg_get_dlg_params()
1079 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml_rq_dlg_get_dlg_params()
1086 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml_rq_dlg_get_dlg_params()
1120 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); in dml_rq_dlg_get_dlg_params()
1166 if (htotal <= 75) { in dml_rq_dlg_get_dlg_params()
1485 (unsigned int) (dst_y_per_row_vblank * (double) htotal in dml_rq_dlg_get_dlg_params()
1495 * (double) htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
[all …]
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| /drivers/gpu/drm/gud/ |
| D | gud_internal.h | 126 dst->htotal = cpu_to_le16(src->htotal); in gud_from_display_mode()
144 dst->htotal = le16_to_cpu(src->htotal); in gud_to_display_mode()
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | head.c | 60 args->v0.htotal = head->arm.htotal; in nvkm_head_mthd_scanoutpos()
68 if (!args->v0.vtotal || !args->v0.htotal) in nvkm_head_mthd_scanoutpos()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 1006 unsigned int htotal = dst->htotal; in dml_rq_dlg_get_dlg_params() local
1136 disp_dlg_regs->refcyc_per_htotal = (unsigned int)(ref_freq_to_pix_freq * (double)htotal in dml_rq_dlg_get_dlg_params()
1144 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double)htotal; in dml_rq_dlg_get_dlg_params()
1193 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml_rq_dlg_get_dlg_params()
1228 - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal in dml_rq_dlg_get_dlg_params()
1235 - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal in dml_rq_dlg_get_dlg_params()
1314 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); in dml_rq_dlg_get_dlg_params()
1356 if (htotal <= 75) { in dml_rq_dlg_get_dlg_params()
1672 (unsigned int)(dst_y_per_row_vblank * (double)htotal in dml_rq_dlg_get_dlg_params()
1678 * (double)htotal * ref_freq_to_pix_freq in dml_rq_dlg_get_dlg_params()
[all …]
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| /drivers/video/fbdev/matrox/ |
| D | matroxfb_maven.c | 226 unsigned int htotal, unsigned int vtotal, in matroxfb_PLL_mavenclock() argument
239 scrlen = htotal * (vtotal - 1); in matroxfb_PLL_mavenclock()
240 fwant = htotal * vtotal; in matroxfb_PLL_mavenclock()
244 fwant, fxtal, htotal, vtotal, fmax); in matroxfb_PLL_mavenclock()
277 if (ln > htotal) in matroxfb_PLL_mavenclock()
299 unsigned int htotal, unsigned int vtotal, in matroxfb_mavenclock() argument
305 fvco = matroxfb_PLL_mavenclock(&maven1000_pll, ctl, htotal, vtotal, in, feed, &p, htotal2); in matroxfb_mavenclock()
748 m->htotal = h - 2; in maven_find_exact_clocks()
801 m->regs[0xA0] = m->htotal; in maven_compute_timming()
802 m->regs[0xA1] = m->htotal >> 8; in maven_compute_timming()
[all …]
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| /drivers/gpu/drm/ |
| D | drm_modes.c | 277 drm_mode->htotal = drm_mode->hdisplay + hblank; in drm_cvt_mode()
280 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; in drm_cvt_mode()
311 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; in drm_cvt_mode()
320 tmp = drm_mode->htotal; /* perform intermediate calcs in u64 */ in drm_cvt_mode()
513 drm_mode->htotal = total_pixels; in drm_gtf_mode_complex()
594 dmode->htotal = dmode->hsync_end + vm->hback_porch; in drm_display_mode_from_videomode()
635 vm->hback_porch = dmode->htotal - dmode->hsync_end; in drm_display_mode_to_videomode()
762 if (mode->htotal == 0 || mode->vtotal == 0) in drm_mode_vrefresh()
766 den = mode->htotal * mode->vtotal; in drm_mode_vrefresh()
823 p->crtc_htotal = p->htotal; in drm_mode_set_crtcinfo()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 1010 unsigned int htotal = e2e_pipe_param.pipe.dest.htotal; in dml1_rq_dlg_get_dlg_params() local
1155 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal in dml1_rq_dlg_get_dlg_params()
1172 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; in dml1_rq_dlg_get_dlg_params()
1224 line_time_in_us = (htotal / pclk_freq_in_mhz); in dml1_rq_dlg_get_dlg_params()
1290 if (dst_x_after_scaler >= htotal) { in dml1_rq_dlg_get_dlg_params()
1291 dst_x_after_scaler = dst_x_after_scaler - htotal; in dml1_rq_dlg_get_dlg_params()
1295 DTRACE("DLG: %s: htotal = %d", __func__, htotal); in dml1_rq_dlg_get_dlg_params()
1313 line_o = (double) dst_y_after_scaler + dst_x_after_scaler / (double) htotal; in dml1_rq_dlg_get_dlg_params()
1314 line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal; in dml1_rq_dlg_get_dlg_params()
1488 if (htotal <= 75) { in dml1_rq_dlg_get_dlg_params()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_rq_dlg_calc_31.c | 966 unsigned int htotal = dst->htotal; in dml_rq_dlg_get_dlg_params() local
1074 …disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_po… in dml_rq_dlg_get_dlg_params()
1143 …if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= v… in dml_rq_dlg_get_dlg_params()
1148 …if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_… in dml_rq_dlg_get_dlg_params()
1206 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); in dml_rq_dlg_get_dlg_params()
1220 if (htotal <= 75) { in dml_rq_dlg_get_dlg_params()
1551 …per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_… in dml_rq_dlg_get_dlg_params()
1555 …per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_… in dml_rq_dlg_get_dlg_params()
1559 …er_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_… in dml_rq_dlg_get_dlg_params()
1564 …disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_fre… in dml_rq_dlg_get_dlg_params()
[all …]
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| /drivers/video/fbdev/ |
| D | amifb.c | 761 u_short htotal; /* vmode */ member
1027 #define htotal2hw(htotal) (div8(htotal) - 1) argument
1031 #define hcenter2hw(htotal) (div8(htotal)) argument
1133 u_int htotal, vtotal; in ami_decode_var() local
1222 par->htotal = down8((var->left_margin + par->xres + var->right_margin + in ami_decode_var()
1233 par->diwstop_h = par->htotal - in ami_decode_var()
1244 if (par->diwstop_h >= par->htotal + 8) { in ami_decode_var()
1267 if (par->htotal != PAL_HTOTAL) { in ami_decode_var()
1279 htotal = PAL_HTOTAL>>clk_shift; in ami_decode_var()
1297 if (par->htotal != NTSC_HTOTAL) { in ami_decode_var()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 415 u32 htotal = nvkm_rdvgac(device, 0, 0x06); in nv04_devinit_preinit() local
416 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x01) << 8; in nv04_devinit_preinit()
417 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x20) << 4; in nv04_devinit_preinit()
418 htotal |= (nvkm_rdvgac(device, 0, 0x25) & 0x01) << 10; in nv04_devinit_preinit()
419 htotal |= (nvkm_rdvgac(device, 0, 0x41) & 0x01) << 11; in nv04_devinit_preinit()
420 if (!htotal) { in nv04_devinit_preinit()
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