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Searched refs:hw_crtc_timing (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c294 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; in dce110_stream_encoder_dp_set_stream_attribute() local
295 if (hw_crtc_timing.flags.INTERLACE) { in dce110_stream_encoder_dp_set_stream_attribute()
297 hw_crtc_timing.v_total /= 2; in dce110_stream_encoder_dp_set_stream_attribute()
298 hw_crtc_timing.v_border_top /= 2; in dce110_stream_encoder_dp_set_stream_attribute()
299 hw_crtc_timing.v_addressable /= 2; in dce110_stream_encoder_dp_set_stream_attribute()
300 hw_crtc_timing.v_border_bottom /= 2; in dce110_stream_encoder_dp_set_stream_attribute()
301 hw_crtc_timing.v_front_porch /= 2; in dce110_stream_encoder_dp_set_stream_attribute()
302 hw_crtc_timing.v_sync_width /= 2; in dce110_stream_encoder_dp_set_stream_attribute()
305 switch (hw_crtc_timing.pixel_encoding) { in dce110_stream_encoder_dp_set_stream_attribute()
314 if (hw_crtc_timing.flags.Y_ONLY) in dce110_stream_encoder_dp_set_stream_attribute()
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/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c267 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; in enc1_stream_encoder_dp_set_stream_attribute() local
269 if (hw_crtc_timing.flags.INTERLACE) { in enc1_stream_encoder_dp_set_stream_attribute()
271 hw_crtc_timing.v_total /= 2; in enc1_stream_encoder_dp_set_stream_attribute()
272 hw_crtc_timing.v_border_top /= 2; in enc1_stream_encoder_dp_set_stream_attribute()
273 hw_crtc_timing.v_addressable /= 2; in enc1_stream_encoder_dp_set_stream_attribute()
274 hw_crtc_timing.v_border_bottom /= 2; in enc1_stream_encoder_dp_set_stream_attribute()
275 hw_crtc_timing.v_front_porch /= 2; in enc1_stream_encoder_dp_set_stream_attribute()
276 hw_crtc_timing.v_sync_width /= 2; in enc1_stream_encoder_dp_set_stream_attribute()
281 switch (hw_crtc_timing.pixel_encoding) { in enc1_stream_encoder_dp_set_stream_attribute()
288 if (hw_crtc_timing.flags.Y_ONLY) in enc1_stream_encoder_dp_set_stream_attribute()
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Ddcn10_optc.c1325 struct dc_crtc_timing *hw_crtc_timing) in optc1_get_hw_timing() argument
1329 if (tg == NULL || hw_crtc_timing == NULL) in optc1_get_hw_timing()
1334 hw_crtc_timing->h_total = s.h_total + 1; in optc1_get_hw_timing()
1335 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); in optc1_get_hw_timing()
1336 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; in optc1_get_hw_timing()
1337 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; in optc1_get_hw_timing()
1339 hw_crtc_timing->v_total = s.v_total + 1; in optc1_get_hw_timing()
1340 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); in optc1_get_hw_timing()
1341 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; in optc1_get_hw_timing()
1342 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; in optc1_get_hw_timing()
Ddcn10_hw_sequencer.c2020 struct dc_crtc_timing hw_crtc_timing[MAX_PIPES] = {0}; in dcn10_align_pixel_clocks() local
2046 &hw_crtc_timing[i]); in dcn10_align_pixel_clocks()
2051 hw_crtc_timing[i].pix_clk_100hz = pclk; in dcn10_align_pixel_clocks()
2061 hw_crtc_timing[i].h_total* in dcn10_align_pixel_clocks()
2062 hw_crtc_timing[i].v_total; in dcn10_align_pixel_clocks()
Ddcn10_optc.h589 struct dc_crtc_timing *hw_crtc_timing);
/drivers/gpu/drm/amd/display/dc/core/
Ddc.c1371 struct dc_crtc_timing hw_crtc_timing = {0}; in dc_validate_seamless_boot_timing() local
1413 if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing)) in dc_validate_seamless_boot_timing()
1416 if (crtc_timing->h_total != hw_crtc_timing.h_total) in dc_validate_seamless_boot_timing()
1419 if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left) in dc_validate_seamless_boot_timing()
1422 if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable) in dc_validate_seamless_boot_timing()
1425 if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right) in dc_validate_seamless_boot_timing()
1428 if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch) in dc_validate_seamless_boot_timing()
1431 if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width) in dc_validate_seamless_boot_timing()
1434 if (crtc_timing->v_total != hw_crtc_timing.v_total) in dc_validate_seamless_boot_timing()
1437 if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top) in dc_validate_seamless_boot_timing()
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/drivers/gpu/drm/amd/display/dc/inc/hw/
Dtiming_generator.h281 struct dc_crtc_timing *hw_crtc_timing);