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/drivers/staging/media/atomisp/pci/
Disp2401_input_system_private.h139 u32 i; in ibuf_ctrl_get_state() local
150 for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { in ibuf_ctrl_get_state()
153 i, in ibuf_ctrl_get_state()
154 &state->proc_state[i]); in ibuf_ctrl_get_state()
162 u32 i; in ibuf_ctrl_dump_state() local
172 for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { in ibuf_ctrl_dump_state()
173 ia_css_print("IBUF controller ID %d Process ID %d num_items 0x%x\n", ID, i, in ibuf_ctrl_dump_state()
174 state->proc_state[i].num_items); in ibuf_ctrl_dump_state()
175 ia_css_print("IBUF controller ID %d Process ID %d num_stores 0x%x\n", ID, i, in ibuf_ctrl_dump_state()
176 state->proc_state[i].num_stores); in ibuf_ctrl_dump_state()
[all …]
/drivers/gpu/drm/nouveau/
Dnouveau_reg.h40 #define NV10_PFB_TILE(i) (0x00100240 + (i*16)) argument
42 #define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16)) argument
43 #define NV10_PFB_TSIZE(i) (0x00100248 + (i*16)) argument
44 #define NV10_PFB_TSTATUS(i) (0x0010024c + (i*16)) argument
49 #define NV20_PFB_ZCOMP(i) (0x00100300 + 4*(i)) argument
55 #define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i)) argument
56 #define NV40_PFB_TILE(i) (0x00100600 + (i*16)) argument
59 #define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16)) argument
60 #define NV40_PFB_TSIZE(i) (0x00100608 + (i*16)) argument
61 #define NV40_PFB_TSTATUS(i) (0x0010060c + (i*16)) argument
[all …]
/drivers/clk/hisilicon/
Dclk.c95 int i; in hisi_clk_register_fixed_rate() local
97 for (i = 0; i < nums; i++) { in hisi_clk_register_fixed_rate()
98 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
99 clks[i].parent_name, in hisi_clk_register_fixed_rate()
100 clks[i].flags, in hisi_clk_register_fixed_rate()
101 clks[i].fixed_rate); in hisi_clk_register_fixed_rate()
104 __func__, clks[i].name); in hisi_clk_register_fixed_rate()
107 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_rate()
113 while (i--) in hisi_clk_register_fixed_rate()
114 clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); in hisi_clk_register_fixed_rate()
[all …]
/drivers/clk/mmp/
Dclk.c30 int i; in mmp_register_fixed_rate_clks() local
33 for (i = 0; i < size; i++) { in mmp_register_fixed_rate_clks()
34 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
35 clks[i].parent_name, in mmp_register_fixed_rate_clks()
36 clks[i].flags, in mmp_register_fixed_rate_clks()
37 clks[i].fixed_rate); in mmp_register_fixed_rate_clks()
40 __func__, clks[i].name); in mmp_register_fixed_rate_clks()
43 if (clks[i].id) in mmp_register_fixed_rate_clks()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
53 int i; in mmp_register_fixed_factor_clks() local
[all …]
/drivers/gpu/drm/amd/display/dc/calcs/
Dcalcs_logger.h186 int i, j, k; in print_bw_calcs_data() local
382 for (i = 0; i < maximum_number_of_surfaces; i++) { in print_bw_calcs_data()
383 DC_LOG_BANDWIDTH_CALCS(" [bool] fbc_en[%d]:%d\n", i, data->fbc_en[i]); in print_bw_calcs_data()
384 DC_LOG_BANDWIDTH_CALCS(" [bool] lpt_en[%d]:%d", i, data->lpt_en[i]); in print_bw_calcs_data()
385 DC_LOG_BANDWIDTH_CALCS(" [bool] displays_match_flag[%d]:%d", i, data->displays_match_flag[i]); in print_bw_calcs_data()
386 DC_LOG_BANDWIDTH_CALCS(" [bool] use_alpha[%d]:%d", i, data->use_alpha[i]); in print_bw_calcs_data()
387 DC_LOG_BANDWIDTH_CALCS(" [bool] orthogonal_rotation[%d]:%d", i, data->orthogonal_rotation[i]); in print_bw_calcs_data()
388 DC_LOG_BANDWIDTH_CALCS(" [bool] enable[%d]:%d", i, data->enable[i]); in print_bw_calcs_data()
389 …LOG_BANDWIDTH_CALCS(" [bool] access_one_channel_only[%d]:%d", i, data->access_one_channel_only[i]); in print_bw_calcs_data()
391 i, data->scatter_gather_enable_for_pipe[i]); in print_bw_calcs_data()
[all …]
/drivers/isdn/mISDN/
Ddsp_audio.c77 int i; in alaw2linear() local
81 i = ((alaw & 0x0F) << 4) + 8 /* rounding error */; in alaw2linear()
84 i = (i + 0x100) << (seg - 1); in alaw2linear()
85 return (short int) ((alaw & 0x80) ? i : -i); in alaw2linear()
143 int i; in dsp_audio_generate_law_tables() local
144 for (i = 0; i < 256; i++) in dsp_audio_generate_law_tables()
145 dsp_audio_alaw_to_s32[i] = alaw2linear(bitrev8((u8)i)); in dsp_audio_generate_law_tables()
147 for (i = 0; i < 256; i++) in dsp_audio_generate_law_tables()
148 dsp_audio_ulaw_to_s32[i] = ulaw2linear(bitrev8((u8)i)); in dsp_audio_generate_law_tables()
150 for (i = 0; i < 256; i++) { in dsp_audio_generate_law_tables()
[all …]
/drivers/media/platform/allegro-dvt/
Dallegro-mail.c46 unsigned int i = 0; in allegro_enc_init() local
49 dst[i++] = msg->reserved0; in allegro_enc_init()
50 dst[i++] = msg->suballoc_dma; in allegro_enc_init()
51 dst[i++] = msg->suballoc_size; in allegro_enc_init()
52 dst[i++] = msg->l2_cache[0]; in allegro_enc_init()
53 dst[i++] = msg->l2_cache[1]; in allegro_enc_init()
54 dst[i++] = msg->l2_cache[2]; in allegro_enc_init()
56 dst[i++] = -1; in allegro_enc_init()
57 dst[i++] = 0; in allegro_enc_init()
60 return i * sizeof(*dst); in allegro_enc_init()
[all …]
/drivers/gpu/drm/i915/
Di915_suspend.c38 int i; in intel_save_swf() local
42 for (i = 0; i < 7; i++) { in intel_save_swf()
43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
46 for (i = 0; i < 3; i++) in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
49 for (i = 0; i < 7; i++) in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
52 for (i = 0; i < 16; i++) { in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
[all …]
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_dcb_82599.c30 u8 i = 0; in ixgbe_dcb_config_rx_arbiter_82599() local
41 for (i = 0; i < MAX_USER_PRIORITY; i++) in ixgbe_dcb_config_rx_arbiter_82599()
42 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); in ixgbe_dcb_config_rx_arbiter_82599()
46 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { in ixgbe_dcb_config_rx_arbiter_82599()
47 credit_refill = refill[i]; in ixgbe_dcb_config_rx_arbiter_82599()
48 credit_max = max[i]; in ixgbe_dcb_config_rx_arbiter_82599()
51 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; in ixgbe_dcb_config_rx_arbiter_82599()
53 if (prio_type[i] == prio_link) in ixgbe_dcb_config_rx_arbiter_82599()
56 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); in ixgbe_dcb_config_rx_arbiter_82599()
86 u8 i; in ixgbe_dcb_config_tx_desc_arbiter_82599() local
[all …]
/drivers/net/wireless/ath/ath9k/
Deeprom.c55 u16 i; in ath9k_hw_get_lower_upper_index() local
66 for (i = 0; i < listSize - 1; i++) { in ath9k_hw_get_lower_upper_index()
67 if (pList[i] == target) { in ath9k_hw_get_lower_upper_index()
68 *indexL = *indexR = i; in ath9k_hw_get_lower_upper_index()
71 if (target < pList[i + 1]) { in ath9k_hw_get_lower_upper_index()
72 *indexL = i; in ath9k_hw_get_lower_upper_index()
73 *indexR = (u16) (i + 1); in ath9k_hw_get_lower_upper_index()
83 int i = 0, j, addr; in ath9k_hw_usb_gen_fill_eeprom() local
88 addrdata[i] = AR5416_EEPROM_OFFSET + in ath9k_hw_usb_gen_fill_eeprom()
90 i++; in ath9k_hw_usb_gen_fill_eeprom()
[all …]
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_io_util.c18 int i; in msm_dss_put_clk() local
20 for (i = num_clk - 1; i >= 0; i--) { in msm_dss_put_clk()
21 if (clk_arry[i].clk) in msm_dss_put_clk()
22 clk_put(clk_arry[i].clk); in msm_dss_put_clk()
23 clk_arry[i].clk = NULL; in msm_dss_put_clk()
29 int i, rc = 0; in msm_dss_get_clk() local
31 for (i = 0; i < num_clk; i++) { in msm_dss_get_clk()
32 clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name); in msm_dss_get_clk()
33 rc = PTR_ERR_OR_ZERO(clk_arry[i].clk); in msm_dss_get_clk()
37 clk_arry[i].clk_name, rc); in msm_dss_get_clk()
[all …]
/drivers/net/ethernet/intel/ixgbevf/
Dethtool.c149 u8 i; in ixgbevf_get_regs() local
178 for (i = 0; i < 2; i++) in ixgbevf_get_regs()
179 regs_buff[14 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAL(i)); in ixgbevf_get_regs()
180 for (i = 0; i < 2; i++) in ixgbevf_get_regs()
181 regs_buff[16 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAH(i)); in ixgbevf_get_regs()
182 for (i = 0; i < 2; i++) in ixgbevf_get_regs()
183 regs_buff[18 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDLEN(i)); in ixgbevf_get_regs()
184 for (i = 0; i < 2; i++) in ixgbevf_get_regs()
185 regs_buff[20 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDH(i)); in ixgbevf_get_regs()
186 for (i = 0; i < 2; i++) in ixgbevf_get_regs()
[all …]
/drivers/input/joystick/
Dcobra.c46 int i, j, ret; in cobra_read_packet() local
50 for (i = 0; i < 2; i++) { in cobra_read_packet()
51 r[i] = buf[i] = 0; in cobra_read_packet()
52 t[i] = COBRA_MAX_STROBE; in cobra_read_packet()
62 for (i = 0, w = u ^ v; i < 2 && w; i++, w >>= 2) in cobra_read_packet()
64 if ((w & 0x30) < 0x30 && r[i] < COBRA_LENGTH && t[i] > 0) { in cobra_read_packet()
65 buf[i] |= (__u64)((w >> 5) & 1) << r[i]++; in cobra_read_packet()
66 t[i] = strobe; in cobra_read_packet()
68 } else t[i] = 0; in cobra_read_packet()
76 for (i = 0; i < 2; i++) { in cobra_read_packet()
[all …]
Danalog.c124 int i, j; in analog_decode() local
127 for (i = 0; i < 4; i++) in analog_decode()
128 if (axes[3] < ((initial[3] * ((i << 1) + 1)) >> 3)) { in analog_decode()
129 buttons |= 1 << (i + 14); in analog_decode()
133 for (i = j = 0; i < 6; i++) in analog_decode()
134 if (analog->mask & (0x10 << i)) in analog_decode()
135 input_report_key(dev, analog->buttons[j++], (buttons >> i) & 1); in analog_decode()
138 for (i = 0; i < 4; i++) in analog_decode()
139 input_report_key(dev, analog->buttons[j++], (buttons >> (i + 10)) & 1); in analog_decode()
150 for (i = j = 0; i < 4; i++) in analog_decode()
[all …]
Dgamecon.c137 int i; in gc_n64_send_command() local
139 for (i = 0; i < GC_N64_LENGTH; i++) { in gc_n64_send_command()
140 unsigned char data = (cmd >> i) & 1 ? target : 0; in gc_n64_send_command()
150 int i; in gc_n64_send_stop_bit() local
152 for (i = 0; i < GC_N64_STOP_LENGTH; i++) { in gc_n64_send_stop_bit()
153 unsigned char data = (GC_N64_STOP_BIT >> i) & 1 ? target : 0; in gc_n64_send_stop_bit()
167 int i; in gc_n64_read_packet() local
190 for (i = 0; i < GC_N64_LENGTH; i++) { in gc_n64_read_packet()
193 data[i] = parport_read_status(gc->pd->port); in gc_n64_read_packet()
209 int i, j, s; in gc_n64_process_packet() local
[all …]
Dadi.c127 int t[2], s[2], i; in adi_read_packet() local
130 for (i = 0; i < 2; i++) { in adi_read_packet()
131 adi[i].ret = -1; in adi_read_packet()
132 t[i] = gameport_time(gameport, ADI_MAX_START); in adi_read_packet()
133 s[i] = 0; in adi_read_packet()
144 for (i = 0; i < 2; i++, w >>= 2, x >>= 2) { in adi_read_packet()
145 t[i]--; in adi_read_packet()
146 if ((w & 0x30) && s[i]) { in adi_read_packet()
147 if ((w & 0x30) < 0x30 && adi[i].ret < ADI_MAX_LENGTH && t[i] > 0) { in adi_read_packet()
148 adi[i].data[++adi[i].ret] = w; in adi_read_packet()
[all …]
/drivers/gpu/drm/amd/amdgpu/
Darct_reg_init.c32 uint32_t i; in arct_reg_base_init() local
33 for (i = 0 ; i < MAX_INSTANCE ; ++i) { in arct_reg_base_init()
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in arct_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in arct_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); in arct_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in arct_reg_base_init()
[all …]
/drivers/hid/amd-sfh-hid/
Damd_sfh_client.c37 int i; in amd_sfh_set_report() local
39 for (i = 0; i < cli_data->num_hid_devices; i++) { in amd_sfh_set_report()
40 if (cli_data->hid_sensor_hubs[i] == hid) { in amd_sfh_set_report()
41 cli_data->cur_hid_dev = i; in amd_sfh_set_report()
52 int i; in amd_sfh_get_report() local
54 for (i = 0; i < cli_data->num_hid_devices; i++) { in amd_sfh_get_report()
55 if (cli_data->hid_sensor_hubs[i] == hid) { in amd_sfh_get_report()
61 new->current_index = i; in amd_sfh_get_report()
62 new->sensor_idx = cli_data->sensor_idx[i]; in amd_sfh_get_report()
66 cli_data->report_id[i] = report_id; in amd_sfh_get_report()
[all …]
/drivers/infiniband/core/
Dpacker.c67 int i; in ib_pack() local
69 for (i = 0; i < desc_len; ++i) { in ib_pack()
70 if (desc[i].size_bits <= 32) { in ib_pack()
76 shift = 32 - desc[i].offset_bits - desc[i].size_bits; in ib_pack()
77 if (desc[i].struct_size_bytes) in ib_pack()
78 val = value_read(desc[i].struct_offset_bytes, in ib_pack()
79 desc[i].struct_size_bytes, in ib_pack()
84 mask = cpu_to_be32(((1ull << desc[i].size_bits) - 1) << shift); in ib_pack()
85 addr = (__be32 *) buf + desc[i].offset_words; in ib_pack()
87 } else if (desc[i].size_bits <= 64) { in ib_pack()
[all …]
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu_helper.c52 uint32_t array_size, i; in phm_copy_clock_limits_array() local
60 for (i = 0; i < power_saving_clock_count; i++) in phm_copy_clock_limits_array()
61 table[i] = le32_to_cpu(pptable_array[i]); in phm_copy_clock_limits_array()
74 uint32_t array_size, i; in phm_copy_overdrive_settings_limits_array() local
82 for (i = 0; i < od_setting_count; i++) in phm_copy_overdrive_settings_limits_array()
83 table[i] = le32_to_cpu(pptable_array[i]); in phm_copy_overdrive_settings_limits_array()
113 uint32_t i; in phm_wait_on_register() local
121 for (i = 0; i < hwmgr->usec_timeout; i++) { in phm_wait_on_register()
129 if (i == hwmgr->usec_timeout) in phm_wait_on_register()
159 uint32_t i; in phm_wait_for_register_unequal() local
[all …]
/drivers/infiniband/hw/mthca/
Dmthca_memfree.c66 int i; in mthca_free_icm_pages() local
72 for (i = 0; i < chunk->npages; ++i) in mthca_free_icm_pages()
73 __free_pages(sg_page(&chunk->mem[i]), in mthca_free_icm_pages()
74 get_order(chunk->mem[i].length)); in mthca_free_icm_pages()
79 int i; in mthca_free_icm_coherent() local
81 for (i = 0; i < chunk->npages; ++i) { in mthca_free_icm_coherent()
82 dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length, in mthca_free_icm_coherent()
83 lowmem_page_address(sg_page(&chunk->mem[i])), in mthca_free_icm_coherent()
84 sg_dma_address(&chunk->mem[i])); in mthca_free_icm_coherent()
224 int i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE; in mthca_table_get() local
[all …]
/drivers/block/paride/
Dbpck.c110 { int i; in bpck_write_block() local
116 for (i=0;i<count;i++) { w0(buf[i]); t2(4); } in bpck_write_block()
122 for (i=0;i<count;i++) { w0(buf[i]); t2(4); } in bpck_write_block()
128 for (i=0;i<count;i++) w4(buf[i]); in bpck_write_block()
135 for (i=0;i<count/2;i++) w4w(((u16 *)buf)[i]); in bpck_write_block()
142 for (i=0;i<count/4;i++) w4l(((u32 *)buf)[i]); in bpck_write_block()
151 { int i, l, h; in bpck_read_block() local
157 for (i=0;i<count;i++) { in bpck_read_block()
160 buf[i] = j44(l,h); in bpck_read_block()
167 for(i=0;i<count;i++) { t2(4); buf[i] = r0(); } in bpck_read_block()
[all …]
/drivers/tty/serial/
Dserial_mctrl_gpio.c47 enum mctrl_gpio_idx i; in mctrl_gpio_set() local
55 for (i = 0; i < UART_GPIO_MAX; i++) in mctrl_gpio_set()
56 if (gpios->gpio[i] && mctrl_gpio_flags_is_dir_out(i)) { in mctrl_gpio_set()
57 desc_array[count] = gpios->gpio[i]; in mctrl_gpio_set()
59 mctrl & mctrl_gpios_desc[i].mctrl); in mctrl_gpio_set()
78 enum mctrl_gpio_idx i; in mctrl_gpio_get() local
83 for (i = 0; i < UART_GPIO_MAX; i++) { in mctrl_gpio_get()
84 if (gpios->gpio[i] && !mctrl_gpio_flags_is_dir_out(i)) { in mctrl_gpio_get()
85 if (gpiod_get_value(gpios->gpio[i])) in mctrl_gpio_get()
86 *mctrl |= mctrl_gpios_desc[i].mctrl; in mctrl_gpio_get()
[all …]
/drivers/media/i2c/cx25840/
Dcx25840-vbi.c60 int i; in decode_vps() local
62 for (i = 0; i < 2 * 13; i += 2) { in decode_vps()
63 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]]; in decode_vps()
64 c = (biphase_tbl[p[i + 1]] & 0xf) | in decode_vps()
65 ((biphase_tbl[p[i]] & 0xf) << 4); in decode_vps()
66 dst[i / 2] = c; in decode_vps()
84 int i; in cx25840_g_sliced_fmt() local
94 for (i = 7; i <= 23; i++) { in cx25840_g_sliced_fmt()
96 state->vbi_regs_offset + 0x424 + i - 7); in cx25840_g_sliced_fmt()
98 svbi->service_lines[0][i] = lcr2vbi[v >> 4]; in cx25840_g_sliced_fmt()
[all …]
/drivers/media/pci/cx18/
Dcx18-av-vbi.c106 int i; in decode_vps() local
108 for (i = 0; i < 2 * 13; i += 2) { in decode_vps()
109 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]]; in decode_vps()
110 c = (biphase_tbl[p[i + 1]] & 0xf) | in decode_vps()
111 ((biphase_tbl[p[i]] & 0xf) << 4); in decode_vps()
112 dst[i / 2] = c; in decode_vps()
130 int i; in cx18_av_g_sliced_fmt() local
140 for (i = 7; i <= 23; i++) { in cx18_av_g_sliced_fmt()
141 u8 v = cx18_av_read(cx, 0x424 + i - 7); in cx18_av_g_sliced_fmt()
143 svbi->service_lines[0][i] = lcr2vbi[v >> 4]; in cx18_av_g_sliced_fmt()
[all …]

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