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Searched refs:i915_vma_pin_ww (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/i915/
Di915_vma.h243 i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
256 err = i915_vma_pin_ww(vma, &ww, size, alignment, flags); in i915_vma_pin()
Di915_vma.c873 int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, in i915_vma_pin_ww() function
1049 err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL); in i915_ggtt_pin()
Di915_gem.c940 ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL); in i915_gem_object_ggtt_pin_ww()
Di915_perf.c1989 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH); in emit_oa_config()
/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_execbuffer.c39 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, PIN_USER | PIN_HIGH); in __igt_gpu_reloc()
Di915_gem_mman.c543 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); in make_obj_busy()
1183 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); in __igt_mmap_gpu()
Di915_gem_context.c976 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); in emit_rpcs_query()
980 err = i915_vma_pin_ww(batch, &ww, 0, 0, PIN_USER); in emit_rpcs_query()
/drivers/gpu/drm/i915/gt/
Dintel_renderstate.c179 err = i915_vma_pin_ww(so->vma, &so->ww, 0, 0, PIN_GLOBAL | PIN_HIGH); in intel_renderstate_init()
Dintel_ring_submission.c1244 err = i915_vma_pin_ww(vma, ww, 0, 0, PIN_USER | PIN_HIGH); in gen7_ctx_switch_bb_init()
Dintel_workarounds.c2198 err = i915_vma_pin_ww(vma, &ww, 0, 0, in engine_wa_list_verify()
/drivers/gpu/drm/i915/selftests/
Digt_spinner.c66 ret = i915_vma_pin_ww(*vma, ww, 0, 0, PIN_USER); in igt_spinner_pin_obj()
/drivers/gpu/drm/i915/gem/
Di915_gem_execbuffer.c434 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags); in eb_pin_vma()
443 err = i915_vma_pin_ww(vma, &eb->ww, in eb_pin_vma()
610 err = i915_vma_pin_ww(vma, &eb->ww, in eb_reserve_vma()
2067 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags); in shadow_batch_pin()