| /drivers/i2c/muxes/ |
| D | i2c-mux-gpio.c | 128 unsigned initial_state; in i2c_mux_gpio_probe() local
172 initial_state = mux->data.idle; in i2c_mux_gpio_probe()
175 initial_state = mux->data.values[0]; in i2c_mux_gpio_probe()
183 if (initial_state & BIT(i)) in i2c_mux_gpio_probe()
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| /drivers/gpu/drm/radeon/ |
| D | rv730_dpm.c | 320 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); in rv730_populate_smc_initial_state() local
340 cpu_to_be32(initial_state->low.mclk); in rv730_populate_smc_initial_state()
354 cpu_to_be32(initial_state->low.sclk); in rv730_populate_smc_initial_state()
359 rv770_get_seq_value(rdev, &initial_state->low); in rv730_populate_smc_initial_state()
362 initial_state->low.vddc, in rv730_populate_smc_initial_state()
377 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv730_populate_smc_initial_state()
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| D | cypress_dpm.c | 1241 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state); in cypress_populate_smc_initial_state() local
1265 cpu_to_be32(initial_state->low.mclk); in cypress_populate_smc_initial_state()
1279 cpu_to_be32(initial_state->low.sclk); in cypress_populate_smc_initial_state()
1287 initial_state->low.vddc, in cypress_populate_smc_initial_state()
1293 initial_state->low.vddci, in cypress_populate_smc_initial_state()
1309 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in cypress_populate_smc_initial_state()
1317 initial_state->low.mclk); in cypress_populate_smc_initial_state()
1319 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold) in cypress_populate_smc_initial_state()
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| D | rv770_dpm.c | 1028 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); in rv770_populate_smc_initial_state() local
1051 cpu_to_be32(initial_state->low.mclk); in rv770_populate_smc_initial_state()
1065 cpu_to_be32(initial_state->low.sclk); in rv770_populate_smc_initial_state()
1070 rv770_get_seq_value(rdev, &initial_state->low); in rv770_populate_smc_initial_state()
1073 initial_state->low.vddc, in rv770_populate_smc_initial_state()
1087 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv770_populate_smc_initial_state()
1094 if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold) in rv770_populate_smc_initial_state()
1096 rv740_get_mclk_frequency_ratio(initial_state->low.mclk) | 0x10; in rv770_populate_smc_initial_state()
1100 if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold) in rv770_populate_smc_initial_state()
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| D | ni_dpm.c | 1683 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); in ni_populate_smc_initial_state() local
1707 cpu_to_be32(initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state()
1722 cpu_to_be32(initial_state->performance_levels[0].sclk); in ni_populate_smc_initial_state()
1729 initial_state->performance_levels[0].vddc, in ni_populate_smc_initial_state()
1746 initial_state->performance_levels[0].vddci, in ni_populate_smc_initial_state()
1764 initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state()
1766 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in ni_populate_smc_initial_state()
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| D | si_dpm.c | 4349 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); in si_populate_smc_initial_state() local
4376 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4392 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4400 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4418 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4424 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4425 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4426 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4441 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4443 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
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| /drivers/video/fbdev/riva/ |
| D | rivafb.h | 51 struct riva_regs initial_state; /* initial startup video mode */ member
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| D | fbdev.c | 1046 riva_save_state(par, &par->initial_state); in rivafb_open()
1066 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); in rivafb_release()
1067 riva_load_state(par, &par->initial_state); in rivafb_release()
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| /drivers/scsi/isci/ |
| D | isci.h | 535 u32 initial_state);
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| D | host.c | 148 const struct sci_base_state *state_table, u32 initial_state) in sci_init_sm() argument
152 sm->initial_state_id = initial_state; in sci_init_sm()
153 sm->previous_state_id = initial_state; in sci_init_sm()
154 sm->current_state_id = initial_state; in sci_init_sm()
157 handler = sm->state_table[initial_state].enter_state; in sci_init_sm()
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| /drivers/video/fbdev/nvidia/ |
| D | nv_type.h | 99 RIVA_HW_STATE initial_state; member
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| D | nvidia.c | 999 nvidia_save_vga(par, &par->initial_state); in nvidiafb_open()
1017 nvidia_write_regs(par, &par->initial_state); in nvidiafb_release()
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| /drivers/nvdimm/ |
| D | btt.c | 626 bool idx_set = false, initial_state = true; in log_set_indices() local
690 initial_state = false; in log_set_indices()
694 if (!initial_state && !idx_set) in log_set_indices()
701 if (initial_state) in log_set_indices()
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| /drivers/regulator/ |
| D | of_regulator.c | 315 constraints->initial_state = PM_SUSPEND_MEM; in of_get_regulation_constraints()
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| D | core.c | 1110 rdev->constraints->initial_state); in suspend_set_initial_state()
1450 if (rdev->constraints->initial_state) { in set_machine_constraints()
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| /drivers/gpu/drm/amd/pm/powerplay/ |
| D | si_dpm.c | 4813 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); in si_populate_smc_initial_state() local
4840 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4856 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4864 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4882 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4888 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4889 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4890 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4903 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4905 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
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