Searched refs:lpp (Results 1 – 4 of 4) sorted by relevance
| /drivers/pci/controller/dwc/ |
| D | pcie-intel-gw.c | 86 static inline void pcie_app_wr(struct intel_pcie_port *lpp, u32 ofs, u32 val) in pcie_app_wr() argument
88 writel(val, lpp->app_base + ofs); in pcie_app_wr()
91 static void pcie_app_wr_mask(struct intel_pcie_port *lpp, u32 ofs, in pcie_app_wr_mask() argument
94 pcie_update_bits(lpp->app_base, ofs, mask, val); in pcie_app_wr_mask()
97 static inline u32 pcie_rc_cfg_rd(struct intel_pcie_port *lpp, u32 ofs) in pcie_rc_cfg_rd() argument
99 return dw_pcie_readl_dbi(&lpp->pci, ofs); in pcie_rc_cfg_rd()
102 static inline void pcie_rc_cfg_wr(struct intel_pcie_port *lpp, u32 ofs, u32 val) in pcie_rc_cfg_wr() argument
104 dw_pcie_writel_dbi(&lpp->pci, ofs, val); in pcie_rc_cfg_wr()
107 static void pcie_rc_cfg_wr_mask(struct intel_pcie_port *lpp, u32 ofs, in pcie_rc_cfg_wr_mask() argument
110 pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
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| /drivers/gpu/drm/pl111/ |
| D | pl111_display.c | 132 u32 lpp, vsw, vfp, vbp; in pl111_display_enable() local
150 lpp = mode->vdisplay - 1; in pl111_display_enable()
162 writel(lpp | in pl111_display_enable()
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| /drivers/nvme/target/ |
| D | io-cmd-bdev.c | 15 const u32 lpp = ql->physical_block_size / ql->logical_block_size; in nvmet_bdev_set_limits() local
17 const __le16 lpp0b = to0based(lpp); in nvmet_bdev_set_limits()
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| /drivers/pinctrl/tegra/ |
| D | pinctrl-tegra20.c | 2114 MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
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