/drivers/firewire/ |
D | sbp2.c | 142 static void sbp2_queue_work(struct sbp2_logical_unit *lu, unsigned long delay) in sbp2_queue_work() argument 144 queue_delayed_work(fw_workqueue, &lu->work, delay); in sbp2_queue_work() 179 static const struct device *lu_dev(const struct sbp2_logical_unit *lu) in lu_dev() argument 181 return &lu->tgt->unit->device; in lu_dev() 261 struct sbp2_logical_unit *lu; member 410 struct sbp2_logical_unit *lu = callback_data; in sbp2_status_write() local 428 dev_notice(lu_dev(lu), in sbp2_status_write() 435 spin_lock_irqsave(&lu->tgt->lock, flags); in sbp2_status_write() 436 list_for_each_entry(iter, &lu->orb_list, link) { in sbp2_status_write() 445 spin_unlock_irqrestore(&lu->tgt->lock, flags); in sbp2_status_write() [all …]
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/drivers/net/ethernet/marvell/mvpp2/ |
D | mvpp2_prs.h | 68 #define MVPP2_PRS_TCAM_LU(lu) (lu) argument 69 #define MVPP2_PRS_TCAM_LU_EN(lu) MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_LU(lu)) argument 287 int lu; member
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D | mvpp2_prs.c | 86 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu) in mvpp2_prs_shadow_set() argument 89 priv->prs_shadow[index].lu = lu; in mvpp2_prs_shadow_set() 101 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument 105 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU(lu & MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set() 291 unsigned int lu) in mvpp2_prs_sram_next_lu_set() argument 297 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set() 374 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS) in mvpp2_prs_flow_find() 673 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) in mvpp2_prs_vlan_find() 726 priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN) in mvpp2_prs_vlan_add() 800 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) in mvpp2_prs_double_vlan_find() [all …]
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D | mvpp2.h | 122 #define MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu) (((lu) & 0x3f) << 3) argument 145 #define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f) argument
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D | mvpp2_debugfs.c | 312 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC || in mvpp2_dbgfs_filter_show() 342 seq_printf(s, "%x\n", priv->prs_shadow[entry->tid].lu); in mvpp2_dbgfs_prs_lu_show()
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/drivers/scsi/esas2r/ |
D | esas2r_int.c | 713 esas2r_trace("ae->lu.dwevent: %x", ae->lu.dwevent); in esas2r_lun_event() 714 esas2r_trace("ae->lu.bystate: %x", ae->lu.bystate); in esas2r_lun_event() 720 if (ae->lu.dwevent & VDAAE_LU_LOST) { in esas2r_lun_event() 723 switch (ae->lu.bystate) { in esas2r_lun_event() 739 memcpy(&t->lu_event, &ae->lu, cplen); in esas2r_lun_event() 819 ae->lu.dwevent, in esas2r_ae_complete() 820 ae->lu.id.tgtlun.wtarget_id, in esas2r_ae_complete() 821 ae->lu.id.tgtlun.bylun, in esas2r_ae_complete() 822 ae->lu.bystate); in esas2r_ae_complete() 824 target = ae->lu.id.tgtlun.wtarget_id; in esas2r_ae_complete()
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D | atvda.h | 929 struct atto_vda_ae_lu lu; member
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D | esas2r_main.c | 1451 struct atto_vda_ae_lu *l = &ae->lu; in esas2r_nuxi_ae_data()
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/drivers/scsi/hisi_sas/ |
D | hisi_sas_v3_hw.c | 2828 const struct hisi_sas_debugfs_reg_lu *lu; member 2885 .lu = debugfs_port_reg_lu, 2958 .lu = debugfs_global_reg_lu, 2971 .lu = debugfs_axi_reg_lu, 2988 .lu = debugfs_ras_reg_lu, 3399 const struct hisi_sas_debugfs_reg_lu *lu) in debugfs_to_reg_name_v3_hw() argument 3401 for (; lu->name; lu++) { in debugfs_to_reg_name_v3_hw() 3402 if (off == lu->off - base_off) in debugfs_to_reg_name_v3_hw() 3403 return lu->name; in debugfs_to_reg_name_v3_hw() 3419 reg->lu); in debugfs_print_reg_v3_hw()
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/drivers/gpu/drm/omapdrm/dss/ |
D | sdi.c | 95 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); in sdi_calc_clock_div()
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D | dpi.c | 272 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu); in dpi_dss_clk_calc()
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/drivers/video/fbdev/omap2/omapfb/dss/ |
D | sdi.c | 88 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); in sdi_calc_clock_div()
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D | dpi.c | 256 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu); in dpi_dss_clk_calc()
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/drivers/pci/ |
D | setup-bus.c | 634 u32 l, bu, lu; in pci_setup_bridge_mmio_pref() local 644 bu = lu = 0; in pci_setup_bridge_mmio_pref() 652 lu = upper_32_bits(region.end); in pci_setup_bridge_mmio_pref() 662 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); in pci_setup_bridge_mmio_pref()
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