| /drivers/media/platform/vsp1/ |
| D | vsp1_lut.c | 28 static inline void vsp1_lut_write(struct vsp1_lut *lut, in vsp1_lut_write() argument
40 static int lut_set_table(struct vsp1_lut *lut, struct v4l2_ctrl *ctrl) in lut_set_table() argument
45 dlb = vsp1_dl_body_get(lut->pool); in lut_set_table()
53 spin_lock_irq(&lut->lock); in lut_set_table()
54 swap(lut->lut, dlb); in lut_set_table()
55 spin_unlock_irq(&lut->lock); in lut_set_table()
63 struct vsp1_lut *lut = in lut_s_ctrl() local
68 lut_set_table(lut, ctrl); in lut_s_ctrl()
154 struct vsp1_lut *lut = to_lut(&entity->subdev); in lut_configure_stream() local
156 vsp1_lut_write(lut, dlb, VI6_LUT_CTRL, VI6_LUT_CTRL_EN); in lut_configure_stream()
[all …]
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| /drivers/video/fbdev/ |
| D | macfb.c | 58 unsigned char lut; member
64 unsigned char lut; member
73 unsigned char lut; member
79 unsigned char lut; /* OFFSET: 0x10 */ member
101 unsigned char lut; member
106 unsigned char lut; /* TFBClutWDataReg, offset 0x90018 */ member
114 unsigned char lut; member
167 &dafb_cmap_regs->lut); in dafb_setpalette()
170 &dafb_cmap_regs->lut); in dafb_setpalette()
173 &dafb_cmap_regs->lut); in dafb_setpalette()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_color.c | 101 static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size) in __is_lut_linear() argument
109 if ((lut[i].red != lut[i].green) || (lut[i].green != lut[i].blue)) in __is_lut_linear()
115 delta = lut[i].red - expected; in __is_lut_linear()
126 static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, in __drm_lut_to_dc_gamma() argument
134 r = drm_color_lut_extract(lut[i].red, 16); in __drm_lut_to_dc_gamma()
135 g = drm_color_lut_extract(lut[i].green, 16); in __drm_lut_to_dc_gamma()
136 b = drm_color_lut_extract(lut[i].blue, 16); in __drm_lut_to_dc_gamma()
147 r = drm_color_lut_extract(lut[i].red, 16); in __drm_lut_to_dc_gamma()
148 g = drm_color_lut_extract(lut[i].green, 16); in __drm_lut_to_dc_gamma()
149 b = drm_color_lut_extract(lut[i].blue, 16); in __drm_lut_to_dc_gamma()
[all …]
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| /drivers/gpu/drm/nouveau/dispnv50/ |
| D | lut.c | 32 nv50_lut_load(struct nv50_lut *lut, int buffer, struct drm_property_blob *blob, in nv50_lut_load() argument
36 void __iomem *mem = lut->mem[buffer].object.map.ptr; in nv50_lut_load()
37 const u32 addr = lut->mem[buffer].addr; in nv50_lut_load()
59 nv50_lut_fini(struct nv50_lut *lut) in nv50_lut_fini() argument
62 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) in nv50_lut_fini()
63 nvif_mem_dtor(&lut->mem[i]); in nv50_lut_fini()
68 struct nv50_lut *lut) in nv50_lut_init() argument
72 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) { in nv50_lut_init()
74 size * 8, &lut->mem[i]); in nv50_lut_init()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_surface.c | 256 struct dc_3dlut *lut = container_of(kref, struct dc_3dlut, refcount); in dc_3dlut_func_free() local
258 kvfree(lut); in dc_3dlut_func_free()
263 struct dc_3dlut *lut = kvzalloc(sizeof(*lut), GFP_KERNEL); in dc_create_3dlut_func() local
265 if (lut == NULL) in dc_create_3dlut_func()
268 kref_init(&lut->refcount); in dc_create_3dlut_func()
269 lut->state.raw = 0; in dc_create_3dlut_func()
271 return lut; in dc_create_3dlut_func()
278 void dc_3dlut_func_release(struct dc_3dlut *lut) in dc_3dlut_func_release() argument
280 kref_put(&lut->refcount, dc_3dlut_func_free); in dc_3dlut_func_release()
283 void dc_3dlut_func_retain(struct dc_3dlut *lut) in dc_3dlut_func_retain() argument
[all …]
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| /drivers/gpu/drm/rcar-du/ |
| D | rcar_cmm.c | 32 } lut; member
87 if (!config->lut.table) { in rcar_cmm_setup()
88 if (rcmm->lut.enabled) { in rcar_cmm_setup()
90 rcmm->lut.enabled = false; in rcar_cmm_setup()
97 if (!rcmm->lut.enabled) { in rcar_cmm_setup()
99 rcmm->lut.enabled = true; in rcar_cmm_setup()
102 rcar_cmm_lut_write(rcmm, config->lut.table); in rcar_cmm_setup()
148 rcmm->lut.enabled = false; in rcar_cmm_disable()
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| /drivers/staging/media/atomisp/pci/isp/kernels/bnlm/ |
| D | ia_css_bnlm.host.c | 45 bnlm_lut_encode(struct bnlm_lut *lut, const int32_t *lut_thr, in bnlm_lut_encode() argument
71 lut->thr[0][i] = 0; in bnlm_lut_encode()
72 lut->val[0][i] = 0; in bnlm_lut_encode()
77 lut->thr[0][i] = lut_thr[i]; in bnlm_lut_encode()
78 lut->val[0][i] = lut_val[i]; in bnlm_lut_encode()
80 lut->val[0][i] = lut_val[i]; /* val has one more element than thr */ in bnlm_lut_encode()
87 lut->thr[0][blk_offset + i] = lut->thr[0][i]; in bnlm_lut_encode()
88 lut->val[0][blk_offset + i] = lut->val[0][i]; in bnlm_lut_encode()
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| /drivers/gpio/ |
| D | gpio-adp5520.c | 19 unsigned char lut[ADP5520_MAXGPIOS]; member
40 return !!(reg_val & dev->lut[off]); in adp5520_gpio_get_value()
50 adp5520_set_bits(dev->master, ADP5520_GPIO_OUT, dev->lut[off]); in adp5520_gpio_set_value()
52 adp5520_clr_bits(dev->master, ADP5520_GPIO_OUT, dev->lut[off]); in adp5520_gpio_set_value()
63 dev->lut[off]); in adp5520_gpio_direction_input()
77 dev->lut[off]); in adp5520_gpio_direction_output()
80 dev->lut[off]); in adp5520_gpio_direction_output()
83 dev->lut[off]); in adp5520_gpio_direction_output()
114 dev->lut[gpios++] = 1 << i; in adp5520_gpio_probe()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_color.c | 114 static bool lut_is_legacy(const struct drm_property_blob *lut) in lut_is_legacy() argument
116 return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; in lut_is_legacy()
543 const struct drm_color_lut *lut; in i9xx_load_lut_8() local
550 lut = blob->data; in i9xx_load_lut_8()
554 i9xx_lut_8(&lut[i])); in i9xx_load_lut_8()
572 const struct drm_color_lut *lut = blob->data; in i965_load_lut_10p6() local
578 i965_lut_10p6_ldw(&lut[i])); in i965_load_lut_10p6()
580 i965_lut_10p6_udw(&lut[i])); in i965_load_lut_10p6()
583 intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); in i965_load_lut_10p6()
584 intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); in i965_load_lut_10p6()
[all …]
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| /drivers/power/supply/ |
| D | s3c_adc_battery.c | 142 const struct s3c_adc_bat_thresh *lut; in s3c_adc_bat_get_property() local
150 lut = bat->pdata->lut_noac; in s3c_adc_bat_get_property()
168 lut = bat->pdata->lut_acin; in s3c_adc_bat_get_property()
176 if (full_volt < calc_full_volt(lut->volt, lut->cur, in s3c_adc_bat_get_property()
183 lut_volt1 = calc_full_volt(lut[0].volt, lut[0].cur, in s3c_adc_bat_get_property()
185 lut_volt2 = calc_full_volt(lut[1].volt, lut[1].cur, in s3c_adc_bat_get_property()
188 new_level = (lut[1].level + in s3c_adc_bat_get_property()
189 (lut[0].level - lut[1].level) * in s3c_adc_bat_get_property()
194 new_level = lut[1].level * 1000; in s3c_adc_bat_get_property()
195 lut++; in s3c_adc_bat_get_property()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_util.c | 104 u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL}; in _dpu_hw_setup_scaler3_lut() local
116 lut[0] = scaler3_cfg->dir_lut; in _dpu_hw_setup_scaler3_lut()
122 lut[1] = scaler3_cfg->cir_lut + in _dpu_hw_setup_scaler3_lut()
129 lut[2] = scaler3_cfg->cir_lut + in _dpu_hw_setup_scaler3_lut()
136 lut[3] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3_lut()
143 lut[4] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3_lut()
150 if (!lut[filter]) in _dpu_hw_setup_scaler3_lut()
160 (lut[filter])[lut_offset++]); in _dpu_hw_setup_scaler3_lut()
179 u32 *lut[QSEED3LITE_FILTERS] = {NULL, NULL}; in _dpu_hw_setup_scaler3lite_lut() local
191 lut[0] = scaler3_cfg->sep_lut + in _dpu_hw_setup_scaler3lite_lut()
[all …]
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| D | dpu_hw_catalog.c | 916 {.fl = 4, .lut = 0x357},
917 {.fl = 5, .lut = 0x3357},
918 {.fl = 6, .lut = 0x23357},
919 {.fl = 7, .lut = 0x223357},
920 {.fl = 8, .lut = 0x2223357},
921 {.fl = 9, .lut = 0x22223357},
922 {.fl = 10, .lut = 0x222223357},
923 {.fl = 11, .lut = 0x2222223357},
924 {.fl = 12, .lut = 0x22222223357},
925 {.fl = 13, .lut = 0x222222223357},
[all …]
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| /drivers/gpu/drm/mediatek/ |
| D | mtk_disp_gamma.c | 59 struct drm_color_lut *lut; in mtk_gamma_set_common() local
68 lut = (struct drm_color_lut *)state->gamma_lut->data; in mtk_gamma_set_common()
70 word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + in mtk_gamma_set_common()
71 (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + in mtk_gamma_set_common()
72 ((lut[i].blue >> 6) & LUT_10BIT_MASK); in mtk_gamma_set_common()
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| /drivers/gpu/drm/arm/ |
| D | malidp_crtc.c | 129 struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data; in malidp_generate_gamma_table() local
137 out_start = drm_color_lut_extract(lut[segments[i].start].green, in malidp_generate_gamma_table()
139 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12); in malidp_generate_gamma_table()
154 struct drm_color_lut *lut; in malidp_crtc_atomic_check_gamma() local
172 lut = (struct drm_color_lut *)state->gamma_lut->data; in malidp_crtc_atomic_check_gamma()
174 if (!((lut[i].red == lut[i].green) && in malidp_crtc_atomic_check_gamma()
175 (lut[i].red == lut[i].blue))) in malidp_crtc_atomic_check_gamma()
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| /drivers/gpu/drm/i915/gem/ |
| D | i915_gem_object.c | 120 struct i915_lut_handle *lut, *ln; in i915_gem_close_object() local
124 list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { in i915_gem_close_object()
125 struct i915_gem_context *ctx = lut->ctx; in i915_gem_close_object()
129 list_move(&lut->obj_link, &close); in i915_gem_close_object()
147 list_for_each_entry_safe(lut, ln, &close, obj_link) { in i915_gem_close_object()
148 struct i915_gem_context *ctx = lut->ctx; in i915_gem_close_object()
157 vma = radix_tree_delete(&ctx->handles_vma, lut->handle); in i915_gem_close_object()
165 i915_gem_context_put(lut->ctx); in i915_gem_close_object()
166 i915_lut_handle_free(lut); in i915_gem_close_object()
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| /drivers/gpu/drm/arm/display/komeda/ |
| D | komeda_color_mgmt.c | 95 struct drm_color_lut *lut; in drm_lut_to_coeffs() local
101 lut = lut_blob->data; in drm_lut_to_coeffs()
108 coeffs[num++] = drm_color_lut_extract(lut[in].red, in drm_lut_to_coeffs()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.h | 83 struct dc_3dlut **lut,
89 struct dc_3dlut **lut,
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| D | dcn30_mpc.c | 987 const struct dc_rgb *lut, in mpc3_set3dlut_ram12() argument
995 red = lut[i].red<<4; in mpc3_set3dlut_ram12()
996 green = lut[i].green<<4; in mpc3_set3dlut_ram12()
997 blue = lut[i].blue<<4; in mpc3_set3dlut_ram12()
998 red1 = lut[i+1].red<<4; in mpc3_set3dlut_ram12()
999 green1 = lut[i+1].green<<4; in mpc3_set3dlut_ram12()
1000 blue1 = lut[i+1].blue<<4; in mpc3_set3dlut_ram12()
1018 const struct dc_rgb *lut, in mpc3_set3dlut_ram10() argument
1026 red = lut[i].red; in mpc3_set3dlut_ram10()
1027 green = lut[i].green; in mpc3_set3dlut_ram10()
[all …]
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| D | dcn30_dpp.c | 1237 const struct dc_rgb *lut, in dpp3_set3dlut_ram12() argument
1244 red = lut[i].red<<4; in dpp3_set3dlut_ram12()
1245 green = lut[i].green<<4; in dpp3_set3dlut_ram12()
1246 blue = lut[i].blue<<4; in dpp3_set3dlut_ram12()
1247 red1 = lut[i+1].red<<4; in dpp3_set3dlut_ram12()
1248 green1 = lut[i+1].green<<4; in dpp3_set3dlut_ram12()
1249 blue1 = lut[i+1].blue<<4; in dpp3_set3dlut_ram12()
1271 const struct dc_rgb *lut, in dpp3_set3dlut_ram10() argument
1278 red = lut[i].red; in dpp3_set3dlut_ram10()
1279 green = lut[i].green; in dpp3_set3dlut_ram10()
[all …]
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| /drivers/clk/tegra/ |
| D | clk-dfll.c | 303 unsigned lut[MAX_DFLL_VOLTAGES]; member
690 td->lut[lut_index]); in dfll_load_i2c_lut()
1660 td->lut[i] = i; in dfll_build_pwm_lut()
1704 int j, selector, lut; in dfll_build_i2c_lut() local
1707 lut = find_vdd_map_entry_exact(td, v); in dfll_build_i2c_lut()
1708 if (lut < 0) in dfll_build_i2c_lut()
1710 td->lut[0] = lut; in dfll_build_i2c_lut()
1734 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
1735 td->lut[j++] = selector; in dfll_build_i2c_lut()
1742 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dpp_cm.c | 996 const struct dc_rgb *lut, in dpp20_set3dlut_ram12() argument
1003 red = lut[i].red<<4; in dpp20_set3dlut_ram12()
1004 green = lut[i].green<<4; in dpp20_set3dlut_ram12()
1005 blue = lut[i].blue<<4; in dpp20_set3dlut_ram12()
1006 red1 = lut[i+1].red<<4; in dpp20_set3dlut_ram12()
1007 green1 = lut[i+1].green<<4; in dpp20_set3dlut_ram12()
1008 blue1 = lut[i+1].blue<<4; in dpp20_set3dlut_ram12()
1030 const struct dc_rgb *lut, in dpp20_set3dlut_ram10() argument
1037 red = lut[i].red; in dpp20_set3dlut_ram10()
1038 green = lut[i].green; in dpp20_set3dlut_ram10()
[all …]
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| /drivers/net/ethernet/intel/iavf/ |
| D | iavf_prototype.h | 44 bool pf_lut, u8 *lut, u16 lut_size);
46 bool pf_lut, u8 *lut, u16 lut_size);
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| /drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_audio.c | 31 struct hdmi_msm_audio_acr lut[MSM_HDMI_SAMPLE_RATE_MAX]; member
118 n = arcs->lut[audio->rate].n; in msm_hdmi_audio_update()
119 cts = arcs->lut[audio->rate].cts; in msm_hdmi_audio_update()
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| /drivers/pci/controller/dwc/ |
| D | pci-layerscape.c | 48 void __iomem *lut; member
108 state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> in ls_pcie_link_up()
263 pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset; in ls_pcie_probe()
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| /drivers/gpu/drm/ |
| D | drm_color_mgmt.c | 598 int drm_color_lut_check(const struct drm_property_blob *lut, u32 tests) in drm_color_lut_check() argument
603 if (!lut || !tests) in drm_color_lut_check()
606 entry = lut->data; in drm_color_lut_check()
607 for (i = 0; i < drm_color_lut_size(lut); i++) { in drm_color_lut_check()
|