| /drivers/iio/adc/ |
| D | dln2-adc.c | 450 #define DLN2_ADC_CHAN(lval, idx) { \ argument
451 lval.type = IIO_VOLTAGE; \
452 lval.channel = idx; \
453 lval.indexed = 1; \
454 lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW); \
455 lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
457 lval.scan_index = idx; \
458 lval.scan_type.sign = 'u'; \
459 lval.scan_type.realbits = DLN2_ADC_DATA_BITS; \
460 lval.scan_type.storagebits = 16; \
[all …]
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| /drivers/cpufreq/ |
| D | qcom-cpufreq-hw.c | 153 u32 data, src, lval, i, core_count, prev_freq = 0, freq; in qcom_cpufreq_hw_read_lut() local
191 lval = FIELD_GET(LUT_L_VAL, data); in qcom_cpufreq_hw_read_lut()
199 freq = xo_rate * lval / 1000; in qcom_cpufreq_hw_read_lut()
276 unsigned int lval; in qcom_lmh_get_throttle_freq() local
279 lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff; in qcom_lmh_get_throttle_freq()
281 lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff; in qcom_lmh_get_throttle_freq()
283 return lval * xo_rate; in qcom_lmh_get_throttle_freq()
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| /drivers/misc/cardreader/ |
| D | rts5261.c | 380 u32 lval, i; in rts5261_init_from_hw() local
404 retval = pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval); in rts5261_init_from_hw()
407 pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval); in rts5261_init_from_hw()
409 valid = (u8)((lval >> 16) & 0x03); in rts5261_init_from_hw()
416 pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval); in rts5261_init_from_hw()
417 lval = lval & 0x00FFFFFF; in rts5261_init_from_hw()
418 retval = pci_write_config_dword(pdev, PCR_SETTING_REG2, lval); in rts5261_init_from_hw()
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| D | rtsx_pcr.c | 1421 u32 lval; in rtsx_pci_init_chip() local
1508 pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval); in rtsx_pci_init_chip()
1510 if (lval & PCI_L1SS_CTL1_ASPM_L1_1) in rtsx_pci_init_chip()
1515 if (lval & PCI_L1SS_CTL1_ASPM_L1_2) in rtsx_pci_init_chip()
1520 if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) in rtsx_pci_init_chip()
1525 if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) in rtsx_pci_init_chip()
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| /drivers/infiniband/hw/qib/ |
| D | qib_driver.c | 452 u64 lval; in qib_kreceive() local
540 lval = l; in qib_kreceive()
542 dd->f_update_usrhead(rcd, lval, updegr, etail, i); in qib_kreceive()
581 lval = (u64)rcd->head | dd->rhdrhead_intr_off; in qib_kreceive()
582 dd->f_update_usrhead(rcd, lval, updegr, etail, i); in qib_kreceive()
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| /drivers/interconnect/qcom/ |
| D | osm-l3.c | 208 u32 info, src, lval, i, prev_freq = 0, freq; in qcom_osm_l3_probe() local
258 lval = FIELD_GET(LUT_L_VAL, info); in qcom_osm_l3_probe()
260 freq = xo_rate * lval; in qcom_osm_l3_probe()
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| /drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_x550.c | 1958 u32 lval, sval, flx_val; in ixgbe_setup_sgmii() local
1963 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); in ixgbe_setup_sgmii()
1967 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; in ixgbe_setup_sgmii()
1968 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; in ixgbe_setup_sgmii()
1969 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; in ixgbe_setup_sgmii()
1970 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; in ixgbe_setup_sgmii()
1971 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; in ixgbe_setup_sgmii()
1974 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); in ixgbe_setup_sgmii()
2030 u32 lval, sval, flx_val; in ixgbe_setup_sgmii_fw() local
2035 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); in ixgbe_setup_sgmii_fw()
[all …]
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| /drivers/comedi/drivers/ |
| D | me4000.c | 927 unsigned short lval; in me4000_ai_isr() local
954 lval = me4000_ai_get_sample(dev, s); in me4000_ai_isr()
955 if (!comedi_buf_write_samples(s, &lval, 1)) in me4000_ai_isr()
974 lval = me4000_ai_get_sample(dev, s); in me4000_ai_isr()
975 if (!comedi_buf_write_samples(s, &lval, 1)) in me4000_ai_isr()
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| /drivers/media/i2c/ |
| D | tda1997x.c | 384 long lval = 0; in io_read16() local
389 lval |= (val << 8); in io_read16()
393 lval |= val; in io_read16()
395 return lval; in io_read16()
401 long lval = 0; in io_read24() local
406 lval |= (val << 16); in io_read24()
410 lval |= (val << 8); in io_read24()
414 lval |= val; in io_read24()
416 return lval; in io_read24()
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| /drivers/net/ethernet/dec/tulip/ |
| D | de4x5.c | 5380 u32 lval[36]; in de4x5_siocdevprivate() member
5457 tmp.lval[0] = inl(DE4X5_STS); j+=4; in de4x5_siocdevprivate()
5458 tmp.lval[1] = inl(DE4X5_BMR); j+=4; in de4x5_siocdevprivate()
5459 tmp.lval[2] = inl(DE4X5_IMR); j+=4; in de4x5_siocdevprivate()
5460 tmp.lval[3] = inl(DE4X5_OMR); j+=4; in de4x5_siocdevprivate()
5461 tmp.lval[4] = inl(DE4X5_SISR); j+=4; in de4x5_siocdevprivate()
5462 tmp.lval[5] = inl(DE4X5_SICR); j+=4; in de4x5_siocdevprivate()
5463 tmp.lval[6] = inl(DE4X5_STRR); j+=4; in de4x5_siocdevprivate()
5464 tmp.lval[7] = inl(DE4X5_SIGR); j+=4; in de4x5_siocdevprivate()
5466 if (copy_to_user(ioc->data, tmp.lval, ioc->len)) in de4x5_siocdevprivate()
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| /drivers/staging/rts5208/ |
| D | rtsx_chip.c | 698 u32 lval = 0; in rts5288_init() local
728 retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval); in rts5288_init()
732 max_func = (u8)((lval >> 29) & 0x07); in rts5288_init()
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