Home
last modified time | relevance | path

Searched refs:mX (Results 1 – 9 of 9) sorted by relevance

/drivers/video/fbdev/omap2/omapfb/dss/
Dpll.c252 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0, in dss_pll_write_config_type_a()
255 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0, in dss_pll_write_config_type_a()
261 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0, in dss_pll_write_config_type_a()
264 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0, in dss_pll_write_config_type_a()
309 l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */ in dss_pll_write_config_type_a()
310 l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */ in dss_pll_write_config_type_a()
312 l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */ in dss_pll_write_config_type_a()
313 l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */ in dss_pll_write_config_type_a()
317 (cinfo->mX[0] ? BIT(7) : 0) | in dss_pll_write_config_type_a()
318 (cinfo->mX[1] ? BIT(8) : 0) | in dss_pll_write_config_type_a()
[all …]
Dhdmi_pll.c91 pi->mX[0] = m2; in hdmi_pll_compute()
Ddss.h118 u16 mX[DSS_PLL_MAX_HSDIVS]; member
Ddsi.c1373 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); in dsi_pll_calc_dsi_fck()
1374 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; in dsi_pll_calc_dsi_fck()
1492 cinfo->mX[HSDIV_DISPC], in dsi_dump_dsidev_clocks()
1501 cinfo->mX[HSDIV_DSI], in dsi_dump_dsidev_clocks()
3457 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; in dsi_config_cmd_mode_interleaving()
4430 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; in dsi_cm_calc_hsdiv_cb()
4718 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; in dsi_vm_calc_hsdiv_cb()
Ddpi.c185 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; in dpi_calc_hsdiv_cb()
/drivers/gpu/drm/omapdrm/dss/
Dpll.c319 cinfo->mX[0] = m2; in dss_pll_calc_b()
410 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0, in dss_pll_write_config_type_a()
413 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0, in dss_pll_write_config_type_a()
419 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0, in dss_pll_write_config_type_a()
422 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0, in dss_pll_write_config_type_a()
503 l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */ in dss_pll_write_config_type_a()
504 l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */ in dss_pll_write_config_type_a()
506 l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */ in dss_pll_write_config_type_a()
507 l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */ in dss_pll_write_config_type_a()
511 (cinfo->mX[0] ? BIT(7) : 0) | in dss_pll_write_config_type_a()
[all …]
Ddss.h139 u16 mX[DSS_PLL_MAX_HSDIVS]; member
Ddsi.c909 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); in dsi_pll_calc_dsi_fck()
910 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; in dsi_pll_calc_dsi_fck()
1005 cinfo->mX[HSDIV_DISPC], in dsi_dump_dsi_clocks()
1014 cinfo->mX[HSDIV_DSI], in dsi_dump_dsi_clocks()
2649 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; in dsi_config_cmd_mode_interleaving()
3687 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; in dsi_cm_calc_hsdiv_cb()
3977 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; in dsi_vm_calc_hsdiv_cb()
Ddpi.c183 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; in dpi_calc_hsdiv_cb()