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Searched refs:match_value (Results 1 – 25 of 33) sorted by relevance

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/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_dpipe.c125 struct devlink_dpipe_value *match_value, in mlxsw_sp_erif_entry_prepare() argument
130 entry->match_values = match_value; in mlxsw_sp_erif_entry_prepare()
136 match_value->match = match; in mlxsw_sp_erif_entry_prepare()
137 match_value->value_size = sizeof(u32); in mlxsw_sp_erif_entry_prepare()
138 match_value->value = kmalloc(match_value->value_size, GFP_KERNEL); in mlxsw_sp_erif_entry_prepare()
139 if (!match_value->value) in mlxsw_sp_erif_entry_prepare()
150 kfree(match_value->value); in mlxsw_sp_erif_entry_prepare()
195 struct devlink_dpipe_value match_value, action_value; in mlxsw_sp_dpipe_table_erif_entries_dump() local
204 memset(&match_value, 0, sizeof(match_value)); in mlxsw_sp_dpipe_table_erif_entries_dump()
208 err = mlxsw_sp_erif_entry_prepare(&entry, &match_value, &match, in mlxsw_sp_dpipe_table_erif_entries_dump()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
Dfs_tcp.c32 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_TCP); in accel_fs_tcp_set_ipv4_flow()
34 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, 4); in accel_fs_tcp_set_ipv4_flow()
35 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in accel_fs_tcp_set_ipv4_flow()
38 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in accel_fs_tcp_set_ipv4_flow()
51 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_TCP); in accel_fs_tcp_set_ipv6_flow()
53 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, 6); in accel_fs_tcp_set_ipv6_flow()
54 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in accel_fs_tcp_set_ipv6_flow()
57 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in accel_fs_tcp_set_ipv6_flow()
128 MLX5_SET(fte_match_param, spec->match_value, outer_headers.tcp_dport, in mlx5e_accel_fs_add_sk()
130 MLX5_SET(fte_match_param, spec->match_value, outer_headers.tcp_sport, in mlx5e_accel_fs_add_sk()
Dipsec_fs.c415 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, ip_version); in setup_fte_common()
419 MLX5_SET(fte_match_param, spec->match_value, outer_headers.frag, 0); in setup_fte_common()
423 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_ESP); in setup_fte_common()
427 MLX5_SET(fte_match_param, spec->match_value, misc_parameters.outer_esp_spi, in setup_fte_common()
431 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in setup_fte_common()
434 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in setup_fte_common()
442 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in setup_fte_common()
445 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in setup_fte_common()
564 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_a, in tx_add_rule()
/drivers/pwm/
Dpwm-omap-dmtimer.c157 u32 load_value, match_value; in pwm_omap_dmtimer_config() local
229 match_value = load_value + duty_cycles - 1; in pwm_omap_dmtimer_config()
232 omap->pdata->set_match(omap->dm_timer, true, match_value); in pwm_omap_dmtimer_config()
235 load_value, load_value, match_value, match_value); in pwm_omap_dmtimer_config()
/drivers/net/ethernet/mellanox/mlx5/core/esw/
Dindir_table.c157 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.ip_version, in mlx5_esw_indir_table_rule_get()
162 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.ethertype, in mlx5_esw_indir_table_rule_get()
172 MLX5_SET(fte_match_param, rule_spec->match_value, in mlx5_esw_indir_table_rule_get()
181 memcpy(MLX5_ADDR_OF(fte_match_param, rule_spec->match_value, in mlx5_esw_indir_table_rule_get()
188 MLX5_SET(fte_match_param, rule_spec->match_value, misc_parameters.vxlan_vni, in mlx5_esw_indir_table_rule_get()
189 MLX5_GET(fte_match_param, spec->match_value, misc_parameters.vxlan_vni)); in mlx5_esw_indir_table_rule_get()
193 MLX5_SET(fte_match_param, rule_spec->match_value, misc_parameters_2.metadata_reg_c_0, in mlx5_esw_indir_table_rule_get()
Dbridge.c433 smac_v = MLX5_ADDR_OF(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_flow_with_esw_create()
442 MLX5_SET(fte_match_param, rule_spec->match_value, misc_parameters_2.metadata_reg_c_0, in mlx5_esw_bridge_ingress_flow_with_esw_create()
451 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_flow_with_esw_create()
455 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.first_vid, in mlx5_esw_bridge_ingress_flow_with_esw_create()
523 smac_v = MLX5_ADDR_OF(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_filter_flow_create()
532 MLX5_SET(fte_match_param, rule_spec->match_value, misc_parameters_2.metadata_reg_c_0, in mlx5_esw_bridge_ingress_filter_flow_create()
537 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_filter_flow_create()
569 dmac_v = MLX5_ADDR_OF(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_egress_flow_create()
584 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_egress_flow_create()
588 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.first_vid, in mlx5_esw_bridge_egress_flow_create()
/drivers/net/ethernet/mellanox/mlx5/core/
Den_arfs.c499 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ethertype, in arfs_add_rule()
513 MLX5_SET(fte_match_param, spec->match_value, outer_headers.tcp_dport, in arfs_add_rule()
515 MLX5_SET(fte_match_param, spec->match_value, outer_headers.tcp_sport, in arfs_add_rule()
522 MLX5_SET(fte_match_param, spec->match_value, outer_headers.udp_dport, in arfs_add_rule()
524 MLX5_SET(fte_match_param, spec->match_value, outer_headers.udp_sport, in arfs_add_rule()
528 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in arfs_add_rule()
532 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in arfs_add_rule()
541 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in arfs_add_rule()
545 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in arfs_add_rule()
Den_fs.c215 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 1); in __mlx5e_add_vlan_rule()
221 MLX5_SET(fte_match_param, spec->match_value, outer_headers.svlan_tag, 1); in __mlx5e_add_vlan_rule()
227 MLX5_SET(fte_match_param, spec->match_value, outer_headers.svlan_tag, 1); in __mlx5e_add_vlan_rule()
230 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, in __mlx5e_add_vlan_rule()
237 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 1); in __mlx5e_add_vlan_rule()
240 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, in __mlx5e_add_vlan_rule()
938 mv_dmac = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5e_add_l2_flow_rule()
Deswitch_offloads.c106 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); in mlx5_eswitch_clear_rule_source_port()
133 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); in mlx5_eswitch_set_rule_source_port()
144 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5_eswitch_set_rule_source_port()
941 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5_eswitch_add_send_to_vport_rule()
1025 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1, in mlx5_eswitch_add_send_to_vport_meta_rules()
1034 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0, in mlx5_eswitch_add_send_to_vport_meta_rules()
1128 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in peer_miss_rules_setup()
1157 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in esw_set_peer_miss_rule_source_port()
1163 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in esw_set_peer_miss_rule_source_port()
1197 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in esw_add_fdb_peer_miss_rules()
[all …]
Drdma.c81 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5_rdma_enable_roce_steering()
Den_tc.c130 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval; in mlx5e_tc_match_to_reg_match()
177 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval; in mlx5e_tc_match_to_reg_get_match()
765 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers); in mlx5e_hairpin_get_prio()
1504 spec->match_value, in mlx5_flow_has_geneve_opt()
1858 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers); in mlx5e_tc_get_ip_version()
1860 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers); in mlx5e_tc_get_ip_version()
2066 return MLX5_ADDR_OF(fte_match_param, spec->match_value, in get_match_inner_headers_value()
2078 return MLX5_ADDR_OF(fte_match_param, spec->match_value, in get_match_outer_headers_value()
2159 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, in __parse_cls_flower()
2163 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, in __parse_cls_flower()
[all …]
Deswitch_offloads_termtbl.c208 port_value = MLX5_GET(fte_match_param, spec->match_value, in mlx5_eswitch_offload_is_uplink_port()
/drivers/net/ethernet/mellanox/mlx5/core/en/
Dtc_tun_geneve.c133 misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_geneve_vni()
170 misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_geneve_options()
172 misc_3_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_3); in mlx5e_tc_tun_parse_geneve_options()
287 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_geneve_params()
Dfs_tt_redirect.c68 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_UDP); in fs_udp_set_dport_flow()
70 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, in fs_udp_set_dport_flow()
73 MLX5_SET(fte_match_param, spec->match_value, outer_headers.udp_dport, udp_dport); in fs_udp_set_dport_flow()
356 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ethertype, ether_type); in fs_any_set_ethertype_flow()
Dtc_tun_gre.c62 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_gretap()
Dtc_tun_mplsoudp.c85 misc2_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, in parse_tunnel()
Dtc_tun_vxlan.c115 misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_vxlan()
Dtc_tun_encap.c64 daddr = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5e_tc_set_attr_rx_tun()
66 saddr = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5e_tc_set_attr_rx_tun()
78 daddr = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5e_tc_set_attr_rx_tun()
80 saddr = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5e_tc_set_attr_rx_tun()
/drivers/clocksource/
Dsh_cmt.c102 u32 match_value; member
459 if (has_wrapped && (new_match > ch->match_value)) { in sh_cmt_clock_event_program_verify()
477 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
488 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
542 ch->total_cycles += ch->match_value + 1; in sh_cmt_interrupt()
568 || (ch->match_value == ch->next_match_value)) in sh_cmt_interrupt()
653 raw += ch->match_value + 1; in sh_cmt_clocksource_read()
924 ch->match_value = ch->max_match_value; in sh_cmt_setup_channel()
/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dfs_ttc.c211 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, proto); in mlx5_generate_ttc_rule()
218 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, ipv); in mlx5_generate_ttc_rule()
222 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ethertype, etype); in mlx5_generate_ttc_rule()
373 MLX5_SET(fte_match_param, spec->match_value, inner_headers.ip_version, ipv); in mlx5_generate_inner_ttc_rule()
379 MLX5_SET(fte_match_param, spec->match_value, inner_headers.ip_protocol, proto); in mlx5_generate_inner_ttc_rule()
/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
Dhelper.c65 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.cvlan_tag); in esw_egress_acl_vlan_create()
67 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vlan_id); in esw_egress_acl_vlan_create()
Dingress_ofld.c35 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 0); in esw_acl_ingress_prio_tag_create()
Dingress_lgcy.c238 spec->match_value, in esw_acl_ingress_lgcy_setup()
/drivers/pci/
Dpci-acpi.c422 u32 match_value; member
540 if ((match_reg & reg->match_mask_and) != reg->match_value) in program_hpx_type3_register()
581 hpx3_reg->match_value = reg_fields[10].integer.value; in parse_hpx3_register()
/drivers/infiniband/hw/mlx5/
Dfs.c201 u32 *match_v = spec->match_value; in parse_flow_attr()
857 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, in set_underlay_qp()
878 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5_ib_set_rule_source_port()
890 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5_ib_set_rule_source_port()
1408 memcpy(spec->match_value, cmd_in, inlen); in _create_raw_flow_rule()

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