| /drivers/gpu/drm/omapdrm/ |
| D | omap_irq.c | 260 unsigned int max_planes; in omap_drm_irq_install() local
269 max_planes = min(ARRAY_SIZE(priv->planes), in omap_drm_irq_install()
271 for (i = 0; i < max_planes; ++i) { in omap_drm_irq_install()
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| /drivers/gpu/drm/tidss/ |
| D | tidss_kms.c | 121 u32 max_planes = feat->num_planes; in tidss_dispc_modeset_init() local
232 while (tidss->num_planes < max_planes) { in tidss_dispc_modeset_init()
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| /drivers/gpu/drm/imx/dcss/ |
| D | dcss-dpr.c | 237 int plane, max_planes = 1; in dcss_dpr_set_res() local
242 max_planes = 2; in dcss_dpr_set_res()
244 for (plane = 0; plane < max_planes; plane++) { in dcss_dpr_set_res()
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 1107 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1109 for (i = 0; i < dc->caps.max_planes; ++i) in dce80_construct()
1307 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1309 for (i = 0; i < dc->caps.max_planes; ++i) in dce81_construct()
1503 dc->caps.max_planes = pool->base.pipe_count; in dce83_construct()
1505 for (i = 0; i < dc->caps.max_planes; ++i) in dce83_construct()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 1096 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1098 for (i = 0; i < dc->caps.max_planes; ++i) in dce60_construct()
1294 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1296 for (i = 0; i < dc->caps.max_planes; ++i) in dce61_construct()
1488 dc->caps.max_planes = pool->base.pipe_count; in dce64_construct()
1490 for (i = 0; i < dc->caps.max_planes; ++i) in dce64_construct()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 1139 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
1141 for (i = 0; i < dc->caps.max_planes; ++i) in dce100_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 1251 dc->caps.max_planes = pool->base.pipe_count; in dce120_resource_construct()
1253 for (i = 0; i < dc->caps.max_planes; ++i) in dce120_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 1390 dc->caps.max_planes = pool->base.pipe_count; in dce112_resource_construct()
1392 for (i = 0; i < dc->caps.max_planes; ++i) in dce112_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 1667 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
1669 for (i = 0; i < dc->caps.max_planes; ++i) in dcn10_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 1749 dc->caps.max_planes = pool->pipe_count; in dcn302_resource_construct()
1751 for (i = 0; i < dc->caps.max_planes; ++i) in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 1680 dc->caps.max_planes = pool->pipe_count; in dcn303_resource_construct()
1682 for (i = 0; i < dc->caps.max_planes; ++i) in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 160 uint32_t max_planes; member
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 2025 dc->caps.max_planes = pool->base.pipe_count; in dcn301_resource_construct()
2027 for (i = 0; i < dc->caps.max_planes; ++i) in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 2258 dc->caps.max_planes = pool->base.pipe_count; in dcn21_resource_construct()
2260 for (i = 0; i < dc->caps.max_planes; ++i) in dcn21_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 2276 dc->caps.max_planes = pool->base.pipe_count; in dcn31_resource_construct()
2278 for (i = 0; i < dc->caps.max_planes; ++i) in dcn31_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 1513 dc->caps.max_planes = pool->base.pipe_count; in dce110_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 2870 dc->caps.max_planes = pool->base.pipe_count; in dcn30_resource_construct()
2872 for (i = 0; i < dc->caps.max_planes; ++i) in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 4038 dc->caps.max_planes = pool->base.pipe_count; in dcn20_resource_construct()
4040 for (i = 0; i < dc->caps.max_planes; ++i) in dcn20_resource_construct()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 4237 for (i = 0; i < dm->dc->caps.max_planes; ++i) { in amdgpu_dm_initialize_drm_device()
|