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Searched refs:md_reg (Results 1 – 10 of 10) sorted by relevance

/drivers/clk/qcom/
Dgcc-msm8660.c102 .md_reg = 0x29d0,
153 .md_reg = 0x29f0,
204 .md_reg = 0x2a10,
255 .md_reg = 0x2a30,
306 .md_reg = 0x2a50,
357 .md_reg = 0x2a70,
408 .md_reg = 0x2a90,
459 .md_reg = 0x2ab0,
508 .md_reg = 0x2ad0,
557 .md_reg = 0x2af0,
[all …]
Dgcc-mdm9615.c186 .md_reg = 0x29d0,
237 .md_reg = 0x29f0,
288 .md_reg = 0x2a10,
339 .md_reg = 0x2a30,
390 .md_reg = 0x2a50,
453 .md_reg = 0x29c8,
502 .md_reg = 0x29e8,
551 .md_reg = 0x2a08,
600 .md_reg = 0x2a28,
649 .md_reg = 0x2a48,
[all …]
Dgcc-ipq806x.c342 .md_reg = 0x29d0,
393 .md_reg = 0x29f0,
444 .md_reg = 0x2a30,
495 .md_reg = 0x2a50,
546 .md_reg = 0x2a70,
597 .md_reg = 0x2a90,
661 .md_reg = 0x29c8,
710 .md_reg = 0x29e8,
759 .md_reg = 0x2a28,
808 .md_reg = 0x2a48,
[all …]
Dgcc-msm8960.c328 .md_reg = 0x29d0,
379 .md_reg = 0x29f0,
430 .md_reg = 0x2a10,
481 .md_reg = 0x2a30,
532 .md_reg = 0x2a50,
583 .md_reg = 0x2a70,
634 .md_reg = 0x2a90,
685 .md_reg = 0x2ab0,
734 .md_reg = 0x2ad0,
783 .md_reg = 0x2af0,
[all …]
Dmmcc-msm8960.c171 .md_reg = 0x0144,
220 .md_reg = 0x0158,
269 .md_reg = 0x0224,
325 .md_reg = 0x0044,
389 .md_reg = 0x0028,
453 .md_reg = 0x022c,
704 .md_reg = 0x0164,
804 .md_reg[0] = 0x0064,
805 .md_reg[1] = 0x0068,
864 .md_reg[0] = 0x0078,
[all …]
Dlcc-ipq806x.c110 .md_reg = 0x4c,
224 .md_reg = 0x58,
304 .md_reg = 0xd0,
363 .md_reg = 0x3c,
Dclk-rcg.c206 u32 md_reg, ns_reg; in configure_bank() local
226 md_reg = rcg->md_reg[new_bank]; in configure_bank()
233 ret = regmap_read(rcg->clkr.regmap, md_reg, &md); in configure_bank()
237 ret = regmap_write(rcg->clkr.regmap, md_reg, md); in configure_bank()
306 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); in clk_dyn_rcg_set_parent()
352 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md); in clk_rcg_recalc_rate()
384 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); in clk_dyn_rcg_recalc_rate()
490 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md); in __clk_rcg_set_rate()
492 regmap_write(rcg->clkr.regmap, rcg->md_reg, md); in __clk_rcg_set_rate()
Dclk-rcg.h77 u32 md_reg; member
112 u32 md_reg[2]; member
Dlcc-mdm9615.c93 .md_reg = 0x4c,
199 .md_reg = _md, \
343 .md_reg = 0x58,
411 .md_reg = 0xd0,
Dlcc-msm8960.c91 .md_reg = 0x4c,
197 .md_reg = _md, \
341 .md_reg = 0x58,
409 .md_reg = 0xd0,