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Searched refs:mdp4_kms (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_kms.c20 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_hw_init() local
21 struct drm_device *dev = mdp4_kms->dev; in mdp4_hw_init()
28 if (mdp4_kms->rev > 1) { in mdp4_hw_init()
29 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); in mdp4_hw_init()
30 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); in mdp4_hw_init()
33 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); in mdp4_hw_init()
36 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); in mdp4_hw_init()
38 clk = clk_get_rate(mdp4_kms->clk); in mdp4_hw_init()
40 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { in mdp4_hw_init()
50 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); in mdp4_hw_init()
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Dmdp4_irq.c23 struct mdp4_kms *mdp4_kms = container_of(irq, struct mdp4_kms, error_handler); in mdp4_irq_error_handler() local
30 struct drm_printer p = drm_info_printer(mdp4_kms->dev->dev); in mdp4_irq_error_handler()
31 drm_state_dump(mdp4_kms->dev, &p); in mdp4_irq_error_handler()
37 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_irq_preinstall() local
38 mdp4_enable(mdp4_kms); in mdp4_irq_preinstall()
39 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); in mdp4_irq_preinstall()
40 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_preinstall()
41 mdp4_disable(mdp4_kms); in mdp4_irq_preinstall()
47 struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); in mdp4_irq_postinstall() local
48 struct mdp_irq *error_handler = &mdp4_kms->error_handler; in mdp4_irq_postinstall()
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Dmdp4_crtc.c62 static struct mdp4_kms *get_kms(struct drm_crtc *crtc) in get_kms()
79 struct mdp4_kms *mdp4_kms = get_kms(crtc); in crtc_flush() local
94 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); in crtc_flush()
119 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base); in unref_cursor_worker() local
120 struct msm_kms *kms = &mdp4_kms->base.base; in unref_cursor_worker()
153 static void setup_mixer(struct mdp4_kms *mdp4_kms) in setup_mixer() argument
155 struct drm_mode_config *config = &mdp4_kms->dev->mode_config; in setup_mixer()
174 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg); in setup_mixer()
180 struct mdp4_kms *mdp4_kms = get_kms(crtc); in blend_setup() local
185 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0); in blend_setup()
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Dmdp4_lcdc_encoder.c27 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) in get_kms()
62 struct mdp4_kms *mdp4_kms = get_kms(encoder); in setup_phy() local
80 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), in setup_phy()
85 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), in setup_phy()
89 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1), in setup_phy()
94 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1), in setup_phy()
98 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2), in setup_phy()
103 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2), in setup_phy()
107 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3), in setup_phy()
112 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3), in setup_phy()
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Dmdp4_dsi_encoder.c21 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) in get_kms()
43 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dsi_encoder_mode_set() local
69 mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL, in mdp4_dsi_encoder_mode_set()
72 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period); in mdp4_dsi_encoder_mode_set()
73 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len); in mdp4_dsi_encoder_mode_set()
74 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL, in mdp4_dsi_encoder_mode_set()
77 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start); in mdp4_dsi_encoder_mode_set()
78 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end); in mdp4_dsi_encoder_mode_set()
80 mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol); in mdp4_dsi_encoder_mode_set()
81 mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR, in mdp4_dsi_encoder_mode_set()
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Dmdp4_dtv_encoder.c22 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) in get_kms()
44 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dtv_encoder_mode_set() local
74 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, in mdp4_dtv_encoder_mode_set()
77 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); in mdp4_dtv_encoder_mode_set()
78 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); in mdp4_dtv_encoder_mode_set()
79 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, in mdp4_dtv_encoder_mode_set()
82 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); in mdp4_dtv_encoder_mode_set()
83 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); in mdp4_dtv_encoder_mode_set()
84 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); in mdp4_dtv_encoder_mode_set()
85 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, in mdp4_dtv_encoder_mode_set()
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Dmdp4_plane.c55 static struct mdp4_kms *get_kms(struct drm_plane *plane) in get_kms()
112 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_cleanup_fb() local
113 struct msm_kms *kms = &mdp4_kms->base.base; in mdp4_plane_cleanup_fb()
158 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_set_scanout() local
159 struct msm_kms *kms = &mdp4_kms->base.base; in mdp4_plane_set_scanout()
162 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe), in mdp4_plane_set_scanout()
166 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe), in mdp4_plane_set_scanout()
170 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe), in mdp4_plane_set_scanout()
172 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe), in mdp4_plane_set_scanout()
174 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe), in mdp4_plane_set_scanout()
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Dmdp4_lvds_pll.c19 static struct mdp4_kms *get_kms(struct mdp4_lvds_pll *lvds_pll) in get_kms()
60 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); in mpd4_lvds_pll_enable() local
69 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33); in mpd4_lvds_pll_enable()
72 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); in mpd4_lvds_pll_enable()
74 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01); in mpd4_lvds_pll_enable()
77 while (!mdp4_read(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_LOCKED)) in mpd4_lvds_pll_enable()
86 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); in mpd4_lvds_pll_disable() local
90 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0); in mpd4_lvds_pll_disable()
91 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); in mpd4_lvds_pll_disable()
Dmdp4_kms.h19 struct mdp4_kms { struct
43 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base) argument
51 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) in mdp4_write() argument
53 msm_writel(data, mdp4_kms->mmio + reg); in mdp4_write()
56 static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg) in mdp4_read() argument
58 return msm_readl(mdp4_kms->mmio + reg); in mdp4_read()
155 int mdp4_disable(struct mdp4_kms *mdp4_kms);
156 int mdp4_enable(struct mdp4_kms *mdp4_kms);
/drivers/gpu/drm/msm/
DMakefile41 disp/mdp4/mdp4_kms.o \