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Searched refs:meta_req_height (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20v2.c375 unsigned int meta_req_height; in get_meta_and_pte_attr() local
496 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
509 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
510 + meta_req_height; in get_meta_and_pte_attr()
511 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
557 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
Ddisplay_rq_dlg_calc_20.c375 unsigned int meta_req_height; in get_meta_and_pte_attr() local
496 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
509 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
510 + meta_req_height; in get_meta_and_pte_attr()
511 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
557 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
/drivers/gpu/drm/amd/display/dc/dml/
Ddml1_display_rq_dlg_calc.c584 unsigned int meta_req_height; in get_surf_rq_param() local
727 meta_req_height = 1 << log2_meta_req_height; in get_surf_rq_param()
741 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_surf_rq_param()
742 + meta_req_height; in get_surf_rq_param()
743 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_surf_rq_param()
784 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_surf_rq_param()
Ddisplay_mode_vba.h606 unsigned int meta_req_height[DC__NUM_DPP__MAX]; member
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c365 unsigned int meta_req_height; in get_meta_and_pte_attr() local
490 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
503 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
504 + meta_req_height; in get_meta_and_pte_attr()
505 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
554 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
Ddisplay_mode_vba_21.c438 unsigned int meta_req_height[],
1964 &locals->meta_req_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2528 locals->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4559 &locals->meta_req_height[k], in dml21_ModeSupportAndSystemConfigurationFull()
5847 unsigned int meta_req_height[], in CalculateMetaAndPTETimes()
5924 - meta_req_height[k]; in CalculateMetaAndPTETimes()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_rq_dlg_calc_31.c428 unsigned int meta_req_height; in get_meta_and_pte_attr() local
570 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
582 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height; in get_meta_and_pte_attr()
583 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
615 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
Ddisplay_mode_vba_31.c484 int meta_req_height[],
2460 &v->meta_req_height[k],
3092 v->meta_req_height,
6060 int meta_req_height[], argument
6130 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c409 unsigned int meta_req_height = 0; in get_meta_and_pte_attr() local
557 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
570 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
571 + meta_req_height; in get_meta_and_pte_attr()
572 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
618 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
Ddisplay_mode_vba_30.c515 int meta_req_height[],
2346 &v->meta_req_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2950 v->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5845 int meta_req_height[], in CalculateMetaAndPTETimes() argument
5915 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k]; in CalculateMetaAndPTETimes()