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Searched refs:meta_req_width (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20v2.c374 unsigned int meta_req_width; in get_meta_and_pte_attr() local
495 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
504 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
505 + meta_req_width; in get_meta_and_pte_attr()
506 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
555 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
Ddisplay_rq_dlg_calc_20.c374 unsigned int meta_req_width; in get_meta_and_pte_attr() local
495 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
504 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
505 + meta_req_width; in get_meta_and_pte_attr()
506 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
555 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
/drivers/gpu/drm/amd/display/dc/dml/
Ddml1_display_rq_dlg_calc.c583 unsigned int meta_req_width; in get_surf_rq_param() local
726 meta_req_width = 1 << log2_meta_req_width; in get_surf_rq_param()
736 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_surf_rq_param()
737 + meta_req_width; in get_surf_rq_param()
738 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_surf_rq_param()
782 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_surf_rq_param()
Ddisplay_mode_vba.h607 unsigned int meta_req_width[DC__NUM_DPP__MAX]; member
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c364 unsigned int meta_req_width; in get_meta_and_pte_attr() local
489 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
498 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
499 + meta_req_width; in get_meta_and_pte_attr()
500 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
552 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
Ddisplay_mode_vba_21.c437 unsigned int meta_req_width[],
1963 &locals->meta_req_width[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2527 locals->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4558 &locals->meta_req_width[k], in dml21_ModeSupportAndSystemConfigurationFull()
5846 unsigned int meta_req_width[], in CalculateMetaAndPTETimes() argument
5921 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in CalculateMetaAndPTETimes()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_rq_dlg_calc_31.c427 unsigned int meta_req_width; in get_meta_and_pte_attr() local
569 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
578 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width; in get_meta_and_pte_attr()
579 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
613 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
Ddisplay_mode_vba_31.c482 int meta_req_width[],
2459 &v->meta_req_width[k],
3090 v->meta_req_width,
6058 int meta_req_width[], argument
6128 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c408 unsigned int meta_req_width = 0; in get_meta_and_pte_attr() local
556 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
565 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
566 + meta_req_width; in get_meta_and_pte_attr()
567 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
616 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
Ddisplay_mode_vba_30.c513 int meta_req_width[],
2345 &v->meta_req_width[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2948 v->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5843 int meta_req_width[], in CalculateMetaAndPTETimes() argument
5913 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in CalculateMetaAndPTETimes()