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Searched refs:mlx5_core_info (Results 1 – 13 of 13) sorted by relevance

/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dcore.h82 mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)
85 mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)
/drivers/net/ethernet/mellanox/mlx5/core/
Dmain.c976 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), in mlx5_function_setup()
1583 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1613 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", in mlx5_pci_err_detected()
1634 mlx5_core_info(dev, in wait_vital()
1653 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", in mlx5_pci_slot_reset()
1676 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", in mlx5_pci_slot_reset()
1759 mlx5_core_info(dev, "Shutdown was called\n"); in shutdown()
Dfw_reset.c212 mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev), in mlx5_fw_live_patch_event()
306 mlx5_core_info(dev, "PCI Link up\n"); in mlx5_pci_link_toggle()
Dlag.c217 mlx5_core_info(dev0, "modify lag map port 1:%d port 2:%d", in mlx5_modify_lag()
241 mlx5_core_info(dev0, "lag map port 1:%d port 2:%d shared_fdb:%d", in mlx5_create_lag()
260 mlx5_core_info(dev0, "Operation mode is single FDB\n"); in mlx5_create_lag()
Dmlx5_core.h91 #define mlx5_core_info(__dev, format, ...) \ macro
Devents.c253 mlx5_core_info(events->dev, in port_module()
Drl.c382 mlx5_core_info(dev, "Rate limit: %u rates are supported, range: %uMbps to %uMbps\n", in mlx5_init_rl_table()
Dhealth.c339 mlx5_core_info(dev, "health recovery succeeded\n"); in mlx5_health_try_recover()
Den_main.c4363 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); in mlx5e_set_netdev_dev_addr()
/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
Dipsec.c538 mlx5_core_info(mdev, "mlx5e: IPSec ESP acceleration enabled\n"); in mlx5e_ipsec_build_netdev()
/drivers/net/ethernet/mellanox/mlx5/core/en/
Dparams.c319 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", in mlx5e_init_rq_type_params()
/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dfs_chains.c743 mlx5_core_info(dev, "Supported tc offload range - chains: %u, prios: %u\n", in mlx5_chains_init()
/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_types.h25 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)