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Searched refs:mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddpcs_3_0_3_offset.h119 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR … macro
Ddpcs_3_0_0_offset.h112 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR … macro
/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_2_1_0_offset.h144 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR … macro
Ddpcs_2_0_0_offset.h136 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR … macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_11_2_d.h10031 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x4978 macro