Home
last modified time | relevance | path

Searched refs:mmRDPCSTX0_RDPCSTX_PHY_CNTL12 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddpcs_3_0_3_offset.h77 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 … macro
Ddpcs_3_0_0_offset.h70 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 … macro
/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_2_1_0_offset.h94 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 … macro
Ddpcs_2_0_0_offset.h94 #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 … macro