Home
last modified time | relevance | path

Searched refs:mmRDPCSTX1_RDPCSTX_PHY_CNTL8 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddpcs_3_0_3_offset.h165 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 … macro
Ddpcs_3_0_0_offset.h158 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 … macro
/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_2_1_0_offset.h194 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 … macro
Ddpcs_2_0_0_offset.h186 #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 … macro