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Searched refs:mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddpcs_3_0_0_offset.h279 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_2_1_0_offset.h327 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX … macro
Ddpcs_2_0_0_offset.h311 #define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX … macro