Home
last modified time | relevance | path

Searched refs:mmRDPCSTX5_RDPCSTX_PHY_CNTL5 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddpcs_3_0_0_offset.h536 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL5 … macro
/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_2_0_0_offset.h602 #define mmRDPCSTX5_RDPCSTX_PHY_CNTL5 … macro