| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | mpc.h | 131 struct mpc { struct
154 struct mpc *mpc, argument
175 struct mpc *mpc,
194 struct mpc *mpc,
206 void (*mpc_init)(struct mpc *mpc);
208 struct mpc *mpc,
222 struct mpc *mpc,
238 struct mpc *mpc,
259 struct mpc *mpc,
277 struct mpc *mpc,
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_mpc.c | 48 struct mpc *mpc, in mpc3_is_dwb_idle() argument
51 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); in mpc3_is_dwb_idle()
63 struct mpc *mpc, in mpc3_set_dwb_mux() argument
67 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); in mpc3_set_dwb_mux()
74 struct mpc *mpc, in mpc3_disable_dwb_mux() argument
77 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); in mpc3_disable_dwb_mux()
84 struct mpc *mpc, in mpc3_set_out_rate_control() argument
90 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); in mpc3_set_out_rate_control()
102 static enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) in mpc3_get_ogam_current() argument
110 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); in mpc3_get_ogam_current()
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| D | dcn30_hwseq.c | 97 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut() local
127 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, in dcn30_set_mpc_shaper_3dlut()
131 result = mpc->funcs->program_3dlut(mpc, in dcn30_set_mpc_shaper_3dlut()
134 result = mpc->funcs->program_shaper(mpc, shaper_lut, in dcn30_set_mpc_shaper_3dlut()
138 mpc->funcs->release_rmu(mpc, mpcc_id); in dcn30_set_mpc_shaper_3dlut()
192 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func() local
200 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { in dcn30_set_output_transfer_func()
207 &mpc->blender_params, false)) in dcn30_set_output_transfer_func()
208 params = &mpc->blender_params; in dcn30_set_output_transfer_func()
215 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); in dcn30_set_output_transfer_func()
[all …]
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| D | dcn30_mpc.h | 777 struct mpc base;
796 struct mpc *mpc,
801 struct mpc *mpc,
805 uint32_t mpcc3_acquire_rmu(struct mpc *mpc,
809 struct mpc *mpc,
814 struct mpc *mpc,
819 struct mpc *mpc,
825 struct mpc *mpc,
831 struct mpc *mpc,
836 struct mpc *mpc,
[all …]
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| D | dcn30_resource.c | 974 static struct mpc *dcn30_mpc_create( in dcn30_mpc_create()
1233 if (pool->base.mpc != NULL) { in dcn30_resource_destruct()
1234 kfree(TO_DCN20_MPC(pool->base.mpc)); in dcn30_resource_destruct()
1235 pool->base.mpc = NULL; in dcn30_resource_destruct()
2630 dc->caps.color.mpc.gamut_remap = 1; in dcn30_resource_construct()
2631 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3 in dcn30_resource_construct()
2632 dc->caps.color.mpc.ogam_ram = 1; in dcn30_resource_construct()
2633 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; in dcn30_resource_construct()
2634 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; in dcn30_resource_construct()
2635 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; in dcn30_resource_construct()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_mpc.c | 40 void mpc1_set_bg_color(struct mpc *mpc, in mpc1_set_bg_color() argument
44 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); in mpc1_set_bg_color()
45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_set_bg_color()
72 struct mpc *mpc, in mpc1_update_blending() argument
76 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); in mpc1_update_blending()
77 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_update_blending()
90 struct mpc *mpc, in mpc1_update_stereo_mix() argument
94 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); in mpc1_update_stereo_mix()
104 void mpc1_assert_idle_mpcc(struct mpc *mpc, int id) in mpc1_assert_idle_mpcc() argument
106 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); in mpc1_assert_idle_mpcc()
[all …]
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| D | dcn10_mpc.h | 125 struct mpc base;
142 struct mpc *mpc,
151 struct mpc *mpc,
156 struct mpc *mpc);
159 struct mpc *mpc,
163 struct mpc *mpc,
167 struct mpc *mpc,
172 struct mpc *mpc,
177 struct mpc *mpc,
181 struct mpc *mpc,
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| D | dcn10_resource.c | 742 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) in dcn10_mpc_create()
976 if (pool->base.mpc != NULL) { in dcn10_resource_destruct()
977 kfree(TO_DCN10_MPC(pool->base.mpc)); in dcn10_resource_destruct()
978 pool->base.mpc = NULL; in dcn10_resource_destruct()
1454 dc->caps.color.mpc.gamut_remap = 0; in dcn10_resource_construct()
1455 dc->caps.color.mpc.num_3dluts = 0; in dcn10_resource_construct()
1456 dc->caps.color.mpc.shared_3d_lut = 0; in dcn10_resource_construct()
1457 dc->caps.color.mpc.ogam_ram = 0; in dcn10_resource_construct()
1458 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; in dcn10_resource_construct()
1459 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; in dcn10_resource_construct()
[all …]
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| D | dcn10_hw_sequencer.c | 338 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s); in dcn10_log_hw_state()
1109 struct mpc *mpc = dc->res_pool->mpc; in dcn10_plane_atomic_disconnect() local
1115 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id); in dcn10_plane_atomic_disconnect()
1121 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove); in dcn10_plane_atomic_disconnect()
1271 dc->res_pool->mpc->funcs->mpc_init_single_inst( in dcn10_init_pipes()
1272 dc->res_pool->mpc, i); in dcn10_init_pipes()
1892 dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc, in dcn10_cursor_lock()
2463 struct mpc *mpc = dc->res_pool->mpc; in dcn10_update_visual_confirm_color() local
2475 if (mpc->funcs->set_bg_color) in dcn10_update_visual_confirm_color()
2476 mpc->funcs->set_bg_color(mpc, color, mpcc_id); in dcn10_update_visual_confirm_color()
[all …]
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| D | dcn10_hw_sequencer_debug.c | 397 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s); in dcn10_get_mpcc_states()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.c | 49 struct mpc *mpc, in mpc2_update_blending() argument
53 struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); in mpc2_update_blending()
55 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc2_update_blending()
74 struct mpc *mpc, in mpc2_set_denorm() argument
78 struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); in mpc2_set_denorm()
112 struct mpc *mpc, in mpc2_set_denorm_clamp() argument
116 struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); in mpc2_set_denorm_clamp()
132 struct mpc *mpc, in mpc2_set_output_csc() argument
138 struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); in mpc2_set_output_csc()
186 struct mpc *mpc, in mpc2_set_ocsc_default() argument
[all …]
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| D | dcn20_mpc.h | 261 struct mpc base;
278 struct mpc *mpc,
283 struct mpc *mpc,
288 struct mpc *mpc,
293 struct mpc *mpc,
299 struct mpc *mpc,
305 struct mpc *mpc,
309 void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
310 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
311 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
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| D | dcn20_hwseq.c | 653 struct mpc *mpc = dc->res_pool->mpc; in dcn20_enable_stream_timing() local
706 if (mpc->funcs->set_out_rate_control) { in dcn20_enable_stream_timing()
708 mpc->funcs->set_out_rate_control( in dcn20_enable_stream_timing()
709 mpc, opp_inst[i], in dcn20_enable_stream_timing()
771 struct mpc *mpc = dc->res_pool->mpc; in dcn20_program_output_csc() local
775 if (mpc->funcs->power_on_mpc_mem_pwr) in dcn20_program_output_csc()
776 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); in dcn20_program_output_csc()
779 if (mpc->funcs->set_output_csc != NULL) in dcn20_program_output_csc()
780 mpc->funcs->set_output_csc(mpc, in dcn20_program_output_csc()
785 if (mpc->funcs->set_ocsc_default != NULL) in dcn20_program_output_csc()
[all …]
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| D | dcn20_resource.c | 1209 struct mpc *dcn20_mpc_create(struct dc_context *ctx) in dcn20_mpc_create()
1477 if (pool->base.mpc != NULL) { in dcn20_resource_destruct()
1478 kfree(TO_DCN20_MPC(pool->base.mpc)); in dcn20_resource_destruct()
1479 pool->base.mpc = NULL; in dcn20_resource_destruct()
3763 dc->caps.color.mpc.gamut_remap = 0; in dcn20_resource_construct()
3764 dc->caps.color.mpc.num_3dluts = 0; in dcn20_resource_construct()
3765 dc->caps.color.mpc.shared_3d_lut = 0; in dcn20_resource_construct()
3766 dc->caps.color.mpc.ogam_ram = 1; in dcn20_resource_construct()
3767 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; in dcn20_resource_construct()
3768 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; in dcn20_resource_construct()
[all …]
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| D | dcn20_resource.h | 110 struct mpc *dcn20_mpc_create(struct dc_context *ctx);
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 783 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) in dcn302_mpc_create()
1156 if (pool->mpc != NULL) { in dcn302_resource_destruct()
1157 kfree(TO_DCN20_MPC(pool->mpc)); in dcn302_resource_destruct()
1158 pool->mpc = NULL; in dcn302_resource_destruct()
1550 dc->caps.color.mpc.gamut_remap = 1; in dcn302_resource_construct()
1551 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 in dcn302_resource_construct()
1552 dc->caps.color.mpc.ogam_ram = 1; in dcn302_resource_construct()
1553 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; in dcn302_resource_construct()
1554 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; in dcn302_resource_construct()
1555 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; in dcn302_resource_construct()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 728 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) in dcn303_mpc_create()
1082 if (pool->mpc != NULL) { in dcn303_resource_destruct()
1083 kfree(TO_DCN20_MPC(pool->mpc)); in dcn303_resource_destruct()
1084 pool->mpc = NULL; in dcn303_resource_destruct()
1493 dc->caps.color.mpc.gamut_remap = 1; in dcn303_resource_construct()
1494 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 in dcn303_resource_construct()
1495 dc->caps.color.mpc.ogam_ram = 1; in dcn303_resource_construct()
1496 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; in dcn303_resource_construct()
1497 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; in dcn303_resource_construct()
1498 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; in dcn303_resource_construct()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 988 static struct mpc *dcn301_mpc_create( in dcn301_mpc_create()
1264 if (pool->base.mpc != NULL) { in dcn301_destruct()
1265 kfree(TO_DCN20_MPC(pool->base.mpc)); in dcn301_destruct()
1266 pool->base.mpc = NULL; in dcn301_destruct()
1809 dc->caps.color.mpc.gamut_remap = 1; in dcn301_resource_construct()
1810 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn301_resource_construct()
1811 dc->caps.color.mpc.ogam_ram = 1; in dcn301_resource_construct()
1812 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; in dcn301_resource_construct()
1813 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; in dcn301_resource_construct()
1814 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; in dcn301_resource_construct()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 935 if (pool->base.mpc != NULL) { in dcn21_resource_destruct()
936 kfree(TO_DCN20_MPC(pool->base.mpc)); in dcn21_resource_destruct()
937 pool->base.mpc = NULL; in dcn21_resource_destruct()
1522 struct mpc *dcn21_mpc_create(struct dc_context *ctx) in dcn21_mpc_create()
2021 dc->caps.color.mpc.gamut_remap = 0; in dcn21_resource_construct()
2022 dc->caps.color.mpc.num_3dluts = 0; in dcn21_resource_construct()
2023 dc->caps.color.mpc.shared_3d_lut = 0; in dcn21_resource_construct()
2024 dc->caps.color.mpc.ogam_ram = 1; in dcn21_resource_construct()
2025 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; in dcn21_resource_construct()
2026 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; in dcn21_resource_construct()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 956 .mpc = false,
1076 static struct mpc *dcn31_mpc_create( in dcn31_mpc_create()
1360 if (pool->base.mpc != NULL) { in dcn31_resource_destruct()
1361 kfree(TO_DCN20_MPC(pool->base.mpc)); in dcn31_resource_destruct()
1362 pool->base.mpc = NULL; in dcn31_resource_destruct()
2044 dc->caps.color.mpc.gamut_remap = 1; in dcn31_resource_construct()
2045 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 in dcn31_resource_construct()
2046 dc->caps.color.mpc.ogam_ram = 1; in dcn31_resource_construct()
2047 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; in dcn31_resource_construct()
2048 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; in dcn31_resource_construct()
[all …]
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 219 struct mpc *mpc; member
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| /drivers/net/ethernet/apple/ |
| D | mace.h | 36 REG(mpc); /* missed packet count (clears when read) */
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| /drivers/net/ethernet/amd/ |
| D | nmclan_cs.c | 349 int mpc; member
1200 pr_debug(" mpc=%d\n", pstats->mpc); in pr_mace_stats()
1229 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC); in update_stats()
1252 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc; in update_stats()
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| /drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| D | cfg80211.h | 467 void brcmf_set_mpc(struct brcmf_if *ndev, int mpc);
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| /drivers/net/ethernet/intel/igc/ |
| D | igc_hw.h | 221 u64 mpc; member
|