| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_mpc.c | 347 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc1_init_mpcc() argument
349 mpcc->mpcc_id = mpcc_inst; in mpc1_init_mpcc()
455 int mpcc_inst, in mpc1_read_mpcc_state() argument
460 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc1_read_mpcc_state()
461 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc1_read_mpcc_state()
462 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc1_read_mpcc_state()
463 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, in mpc1_read_mpcc_state()
467 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, in mpc1_read_mpcc_state()
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| D | dcn10_hw_sequencer.c | 1123 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect()
1308 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn10_init_pipes()
1315 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_init_pipes()
3114 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) in get_hubp_by_inst() argument
3119 if (res_pool->hubps[i]->inst == mpcc_inst) in get_hubp_by_inst()
3132 int mpcc_inst; in dcn10_wait_for_mpcc_disconnect() local
3141 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { in dcn10_wait_for_mpcc_disconnect()
3142 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { in dcn10_wait_for_mpcc_disconnect()
3143 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
3147 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
[all …]
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| D | dcn10_mpc.h | 198 int mpcc_inst,
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| D | dcn10_resource.c | 1175 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_idle_pipe_for_layer()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 229 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
230 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
236 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
251 wb_info->mpcc_inst); in dcn30_update_writeback()
333 wb_info->mpcc_inst); in dcn30_enable_writeback()
397 wb_info.mpcc_inst = -1; in dcn30_program_all_writeback_pipes_in_tree()
405 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
410 if (wb_info.mpcc_inst == -1) { in dcn30_program_all_writeback_pipes_in_tree()
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| D | dcn30_mpc.c | 1038 static void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc3_init_mpcc() argument
1040 mpcc->mpcc_id = mpcc_inst; in mpc3_init_mpcc()
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| D | dcn30_resource.c | 1777 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dmub_psr.c | 280 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | mpc.h | 155 int mpcc_inst,
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.c | 512 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc2_init_mpcc() argument
514 mpcc->mpcc_id = mpcc_inst; in mpc2_init_mpcc()
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| D | dcn20_hwseq.c | 1464 int mpcc_inst = hubp->inst; in dcn20_update_dchubp_dpp() local
1469 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { in dcn20_update_dchubp_dpp()
1470 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); in dcn20_update_dchubp_dpp()
1471 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; in dcn20_update_dchubp_dpp()
2543 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn20_fpga_init_hw()
2553 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn20_fpga_init_hw()
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| D | dcn20_resource.c | 1883 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1968 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in dcn20_split_stream_for_mpc()
3308 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn20_acquire_idle_pipe_for_layer()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 320 uint8_t mpcc_inst; member
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_resource.c | 1331 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_split_pipe()
1712 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_free_pipe()
1969 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; in acquire_resource_from_hw_enabled_state()
1975 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); in acquire_resource_from_hw_enabled_state()
1978 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id; in acquire_resource_from_hw_enabled_state()
1981 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = in acquire_resource_from_hw_enabled_state()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_stream.h | 95 int mpcc_inst; member
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| /drivers/gpu/drm/amd/display/dmub/inc/ |
| D | dmub_cmd.h | 1343 uint8_t mpcc_inst; member
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 539 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in split_stream_across_pipes()
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