| /drivers/clk/ |
| D | clk-vt8500.c | 455 u32 mul; in wm8750_find_pll_bits() local
464 for (mul = 0; mul <= 255; mul++) { in wm8750_find_pll_bits()
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
472 *multiplier = mul; in wm8750_find_pll_bits()
480 *multiplier = mul; in wm8750_find_pll_bits()
503 u32 mul; in wm8850_find_pll_bits() local
512 for (mul = 0; mul <= 127; mul++) { in wm8850_find_pll_bits()
513 tclk = parent_rate * ((mul + 1) * 2) / in wm8850_find_pll_bits()
520 *multiplier = mul; in wm8850_find_pll_bits()
528 *multiplier = mul; in wm8850_find_pll_bits()
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| D | clk-cdce706.c | 73 unsigned mul; member
169 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
172 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
173 u64 res = (u64)parent_rate * hwd->mul; in cdce706_pll_recalc_rate()
189 unsigned long mul, div; in cdce706_pll_round_rate() local
198 &mul, &div); in cdce706_pll_round_rate()
199 hwd->mul = mul; in cdce706_pll_round_rate()
204 __func__, hwd->idx, mul, div); in cdce706_pll_round_rate()
206 res = (u64)*parent_rate * hwd->mul; in cdce706_pll_round_rate()
215 unsigned long mul = hwd->mul, div = hwd->div; in cdce706_pll_set_rate() local
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| D | clk-nomadik.c | 227 u8 mul; in pll_clk_recalc_rate() local
230 mul = (val >> 8) & 0x3FU; in pll_clk_recalc_rate()
231 mul += 2; in pll_clk_recalc_rate()
233 return (parent_rate * mul) >> div; in pll_clk_recalc_rate()
237 u8 mul; in pll_clk_recalc_rate() local
239 mul = (val >> 24) & 0x3FU; in pll_clk_recalc_rate()
240 mul += 2; in pll_clk_recalc_rate()
241 return (parent_rate * mul); in pll_clk_recalc_rate()
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| D | clk-moxart.c | 24 unsigned int mul; in moxart_of_pll_clk_init() local
37 mul = readl(base + 0x30) >> 3 & 0x3f; in moxart_of_pll_clk_init()
46 hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1); in moxart_of_pll_clk_init()
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| /drivers/clk/actions/ |
| D | owl-factor.c | 29 unsigned int val, unsigned int *mul, unsigned int *div) in _get_table_div_mul() argument
35 *mul = clkt->mul; in _get_table_div_mul()
52 calc_rate = parent_rate * clkt->mul; in _get_table_val()
86 try_parent_rate = rate * clkt->div / clkt->mul; in owl_clk_val_best()
90 __func__, clkt->val, clkt->mul, clkt->div, in owl_clk_val_best()
103 cur_rate = DIV_ROUND_UP(parent_rate, clkt->div) * clkt->mul; in owl_clk_val_best()
126 unsigned int val, mul = 0, div = 1; in owl_factor_helper_round_rate() local
129 _get_table_div_mul(clkt, val, &mul, &div); in owl_factor_helper_round_rate()
131 return *parent_rate * mul / div; in owl_factor_helper_round_rate()
150 u32 reg, val, mul, div; in owl_factor_helper_recalc_rate() local
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| D | owl-pll.c | 20 u32 mul; in owl_pll_calculate_mul() local
22 mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq); in owl_pll_calculate_mul()
23 if (mul < pll_hw->min_mul) in owl_pll_calculate_mul()
24 mul = pll_hw->min_mul; in owl_pll_calculate_mul()
25 else if (mul > pll_hw->max_mul) in owl_pll_calculate_mul()
26 mul = pll_hw->max_mul; in owl_pll_calculate_mul()
28 return mul &= mul_mask(pll_hw); in owl_pll_calculate_mul()
65 u32 mul; in owl_pll_round_rate() local
76 mul = owl_pll_calculate_mul(pll_hw, rate); in owl_pll_round_rate()
78 return pll_hw->bfreq * mul; in owl_pll_round_rate()
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| /drivers/clk/at91/ |
| D | clk-pll.c | 40 u16 mul; member
68 u16 mul; in clk_pll_prepare() local
72 mul = PLL_MUL(pllr, layout); in clk_pll_prepare()
76 (div == pll->div && mul == pll->mul)) in clk_pll_prepare()
89 ((pll->mul & layout->mul_mask) << layout->mul_shift)); in clk_pll_prepare()
117 if (!pll->div || !pll->mul) in clk_pll_recalc_rate()
120 return (parent_rate / pll->div) * (pll->mul + 1); in clk_pll_recalc_rate()
125 u32 *div, u32 *mul, in clk_pll_get_best_div_mul() argument
225 if (mul) in clk_pll_get_best_div_mul()
226 *mul = bestmul - 1; in clk_pll_get_best_div_mul()
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| D | clk-sam9x60-pll.c | 42 u16 mul; member
74 return parent_rate * (frac->mul + 1) + in sam9x60_frac_pll_recalc_rate()
95 (cmul == frac->mul && cfrac == frac->frac)) in sam9x60_frac_pll_prepare()
106 (frac->mul << core->layout->mul_shift) | in sam9x60_frac_pll_prepare()
209 frac->mul = nmul - 1; in sam9x60_frac_pll_compute_mul_frac()
254 if (cmul == frac->mul && cfrac == frac->frac) in sam9x60_frac_pll_set_rate_chg()
258 (frac->mul << core->layout->mul_shift) | in sam9x60_frac_pll_set_rate_chg()
546 frac->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val); in sam9x60_clk_register_frac_pll()
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| /drivers/clk/tegra/ |
| D | clk-utils.c | 16 int mul; in div_frac_get() local
21 mul = 1 << frac_width; in div_frac_get()
24 divider_ux1 *= mul; in div_frac_get()
32 divider_ux1 *= mul; in div_frac_get()
34 if (divider_ux1 < mul) in div_frac_get()
37 divider_ux1 -= mul; in div_frac_get()
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| D | clk-divider.c | 40 int div, mul; in clk_frac_div_recalc_rate() local
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
52 div += mul; in clk_frac_div_recalc_rate()
54 rate *= mul; in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_round_rate() local
75 mul = get_mul(divider); in clk_frac_div_round_rate()
77 return DIV_ROUND_UP(output_rate * mul, div + mul); in clk_frac_div_round_rate()
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| D | clk-periph-fixed.c | 57 rate = (unsigned long long)parent_rate * fixed->mul; in tegra_clk_periph_fixed_recalc_rate()
74 unsigned int mul, in tegra_clk_register_periph_fixed() argument
99 fixed->mul = mul; in tegra_clk_register_periph_fixed()
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| /drivers/cpufreq/ |
| D | cpufreq-nforce2.c | 25 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div) argument
69 unsigned char mul, div; in nforce2_calc_fsb() local
71 mul = (pll >> 8) & 0xff; in nforce2_calc_fsb()
75 return NFORCE2_XTAL * mul / div; in nforce2_calc_fsb()
89 unsigned char mul = 0, div = 0; in nforce2_calc_pll() local
93 while (((mul == 0) || (div == 0)) && (tried <= 3)) { in nforce2_calc_pll()
98 mul = xmul; in nforce2_calc_pll()
104 if ((mul == 0) || (div == 0)) in nforce2_calc_pll()
107 return NFORCE2_PLL(mul, div); in nforce2_calc_pll()
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| D | cppc_cpufreq.c | 317 u64 mul, div; in cppc_cpufreq_perf_to_khz() local
320 mul = caps->nominal_freq - caps->lowest_freq; in cppc_cpufreq_perf_to_khz()
322 offset = caps->nominal_freq - div64_u64(caps->nominal_perf * mul, div); in cppc_cpufreq_perf_to_khz()
326 mul = max_khz; in cppc_cpufreq_perf_to_khz()
330 retval = offset + div64_u64(perf * mul, div); in cppc_cpufreq_perf_to_khz()
342 u64 mul, div; in cppc_cpufreq_khz_to_perf() local
345 mul = caps->nominal_perf - caps->lowest_perf; in cppc_cpufreq_khz_to_perf()
347 offset = caps->nominal_perf - div64_u64(caps->nominal_freq * mul, div); in cppc_cpufreq_khz_to_perf()
351 mul = caps->highest_perf; in cppc_cpufreq_khz_to_perf()
355 retval = offset + div64_u64(freq * mul, div); in cppc_cpufreq_khz_to_perf()
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| /drivers/gpu/drm/i915/ |
| D | i915_fixed.h | 75 static inline u32 mul_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t mul) in mul_round_up_u32_fixed16() argument
79 tmp = mul_u32_u32(val, mul.val); in mul_round_up_u32_fixed16()
87 uint_fixed_16_16_t mul) in mul_fixed16()
91 tmp = mul_u32_u32(val.val, mul.val); in mul_fixed16()
118 static inline uint_fixed_16_16_t mul_u32_fixed16(u32 val, uint_fixed_16_16_t mul) in mul_u32_fixed16() argument
122 tmp = mul_u32_u32(val, mul.val); in mul_u32_fixed16()
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| /drivers/net/wireless/ath/ath9k/ |
| D | common.h | 39 #define ATH_EP_MUL(x, mul) ((x) * (mul)) argument
47 #define ATH_EP_RND(x, mul) \ argument
48 (((x) + ((mul)/2)) / (mul))
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| /drivers/pwm/ |
| D | pwm-img.c | 96 unsigned long mul, output_clk_hz, input_clk_hz; in img_pwm_config() local
110 mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz); in img_pwm_config()
111 if (mul <= max_timebase) { in img_pwm_config()
113 timebase = DIV_ROUND_UP(mul, 1); in img_pwm_config()
114 } else if (mul <= max_timebase * 8) { in img_pwm_config()
116 timebase = DIV_ROUND_UP(mul, 8); in img_pwm_config()
117 } else if (mul <= max_timebase * 64) { in img_pwm_config()
119 timebase = DIV_ROUND_UP(mul, 64); in img_pwm_config()
120 } else if (mul <= max_timebase * 512) { in img_pwm_config()
122 timebase = DIV_ROUND_UP(mul, 512); in img_pwm_config()
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| /drivers/media/i2c/ |
| D | ccs-pll.c | 292 struct ccs_pll *pll, u32 mul, u32 div) in __ccs_pll_calculate_vt_tree() argument
308 pll_fr->pll_ip_clk_freq_hz * mul)); in __ccs_pll_calculate_vt_tree()
311 more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul); in __ccs_pll_calculate_vt_tree()
314 pll_fr->pll_multiplier = mul * more_mul; in __ccs_pll_calculate_vt_tree()
409 u32 mul, div; in ccs_pll_calculate_vt_tree() local
413 mul = pre_mul * pll_fr->pre_pll_clk_div / div; in ccs_pll_calculate_vt_tree()
417 pll_fr->pre_pll_clk_div, mul, div); in ccs_pll_calculate_vt_tree()
420 mul, div); in ccs_pll_calculate_vt_tree()
591 struct ccs_pll_branch_bk *op_pll_bk, u32 mul, in ccs_pll_calculate_op() argument
612 more_mul_max = op_lim_fr->max_pll_multiplier / mul; in ccs_pll_calculate_op()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_afmt.c | 54 unsigned long div, mul; in amdgpu_afmt_calc_cts() local
70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts()
72 n *= mul; in amdgpu_afmt_calc_cts()
73 cts *= mul; in amdgpu_afmt_calc_cts()
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| /drivers/clk/imgtec/ |
| D | clk-boston.c | 34 uint mmcmdiv, mul, cpu_div, sys_div; in clk_boston_setup() local
53 mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL); in clk_boston_setup()
56 sys_freq = mult_frac(in_freq, mul, sys_div); in clk_boston_setup()
59 cpu_freq = mult_frac(in_freq, mul, cpu_div); in clk_boston_setup()
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| /drivers/gpu/drm/tegra/ |
| D | hda.c | 14 unsigned int mul, div, bits, channels; in tegra_hda_parse_format() local
26 mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT; in tegra_hda_parse_format()
29 fmt->sample_rate *= (mul + 1) / (div + 1); in tegra_hda_parse_format()
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| D | dsi.c | 45 unsigned int mul; member
481 unsigned int hact, hsw, hbp, hfp, i, mul, div; in tegra_dsi_configure() local
492 mul = state->mul; in tegra_dsi_configure()
539 hact = mode->hdisplay * mul / div; in tegra_dsi_configure()
542 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; in tegra_dsi_configure()
545 hbp = (mode->htotal - mode->hsync_end) * mul / div; in tegra_dsi_configure()
551 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; in tegra_dsi_configure()
564 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); in tegra_dsi_configure()
574 bytes = 1 + (mode->hdisplay / 2) * mul / div; in tegra_dsi_configure()
577 bytes = 1 + mode->hdisplay * mul / div; in tegra_dsi_configure()
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| /drivers/media/radio/si4713/ |
| D | si4713.c | 926 s32 *bit, s32 *mask, u16 *property, int *mul, in si4713_choose_econtrol_action() argument
935 *mul = 1; in si4713_choose_econtrol_action()
939 *mul = 1; in si4713_choose_econtrol_action()
943 *mul = 1; in si4713_choose_econtrol_action()
947 *mul = 1; in si4713_choose_econtrol_action()
951 *mul = ATTACK_TIME_UNIT; in si4713_choose_econtrol_action()
955 *mul = 10; in si4713_choose_econtrol_action()
959 *mul = 10; in si4713_choose_econtrol_action()
963 *mul = 1; in si4713_choose_econtrol_action()
1110 int mul = 0; in si4713_s_ctrl() local
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| /drivers/usb/gadget/udc/bdc/ |
| D | bdc_cmd.c | 139 u32 mps, mbs, mul, si; in bdc_config_ep() local
144 cmd_sc = mul = mbs = param2 = 0; in bdc_config_ep()
165 mul = comp_desc->bmAttributes; in bdc_config_ep()
168 param2 |= mul << EPM_SHIFT; in bdc_config_ep()
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| /drivers/gpu/drm/i915/gt/shaders/clear_kernel/ |
| D | hsw.asm | 53 mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
57 mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
62 mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
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| D | ivb.asm | 53 mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
57 mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
62 mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
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