| /drivers/clk/ |
| D | clk-multiplier.c | 15 static inline u32 clk_mult_readl(struct clk_multiplier *mult) in clk_mult_readl() argument
17 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_readl()
18 return ioread32be(mult->reg); in clk_mult_readl()
20 return readl(mult->reg); in clk_mult_readl()
23 static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) in clk_mult_writel() argument
25 if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) in clk_mult_writel()
26 iowrite32be(val, mult->reg); in clk_mult_writel()
28 writel(val, mult->reg); in clk_mult_writel()
31 static unsigned long __get_mult(struct clk_multiplier *mult, in __get_mult() argument
35 if (mult->flags & CLK_MULTIPLIER_ROUND_CLOSEST) in __get_mult()
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| D | clk-fixed-factor.c | 28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
82 unsigned long flags, unsigned int mult, unsigned int div, in __clk_hw_register_fixed_factor() argument
104 fix->mult = mult; in __clk_hw_register_fixed_factor()
136 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor() argument
139 flags, mult, div, false); in clk_hw_register_fixed_factor()
145 unsigned int mult, unsigned int div) in clk_register_fixed_factor() argument
149 hw = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult, in clk_register_fixed_factor()
183 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor() argument
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| D | clk-gemini.c | 278 unsigned int mult, div; in gemini_clk_probe() local
328 mult = 1; in gemini_clk_probe()
331 mult = 3; in gemini_clk_probe()
334 hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div); in gemini_clk_probe()
359 mult = 1; in gemini_clk_probe()
397 unsigned int mult, div; in gemini_cc_init() local
444 mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK); in gemini_cc_init()
448 mult *= 2; in gemini_cc_init()
449 hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div); in gemini_cc_init()
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| /drivers/clk/sunxi-ng/ |
| D | ccu_mult.c | 14 unsigned long mult, min, max; member
18 struct _ccu_mult *mult) in ccu_mult_find_best() argument
23 if (_mult < mult->min) in ccu_mult_find_best()
24 _mult = mult->min; in ccu_mult_find_best()
26 if (_mult > mult->max) in ccu_mult_find_best()
27 _mult = mult->max; in ccu_mult_find_best()
29 mult->mult = _mult; in ccu_mult_find_best()
41 _cm.min = cm->mult.min; in ccu_mult_round_rate()
43 if (cm->mult.max) in ccu_mult_round_rate()
44 _cm.max = cm->mult.max; in ccu_mult_round_rate()
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| /drivers/clk/renesas/ |
| D | rcar-gen3-cpg.c | 56 unsigned int mult; in cpg_pll_clk_recalc_rate() local
60 mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
69 unsigned int min_mult, max_mult, mult; in cpg_pll_clk_determine_rate() local
78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
79 mult = clamp(mult, min_mult, max_mult); in cpg_pll_clk_determine_rate()
81 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
89 unsigned int mult, i; in cpg_pll_clk_set_rate() local
92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); in cpg_pll_clk_set_rate()
93 mult = clamp(mult, 1U, 128U); in cpg_pll_clk_set_rate()
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| D | rcar-gen2-cpg.c | 57 unsigned int mult; in cpg_z_clk_recalc_rate() local
61 mult = 32 - val; in cpg_z_clk_recalc_rate()
63 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
70 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
77 mult = div64_ul(req->rate * 32ULL, prate); in cpg_z_clk_determine_rate()
78 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
80 req->rate = div_u64((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
88 unsigned int mult; in cpg_z_clk_set_rate() local
92 mult = div64_ul(rate * 32ULL, parent_rate); in cpg_z_clk_set_rate()
93 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
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| D | clk-sh73a0.c | 81 unsigned int mult = 1; in sh73a0_cpg_register_clock() local
112 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
116 mult *= 2; in sh73a0_cpg_register_clock()
124 mult = readl(dsi_reg); in sh73a0_cpg_register_clock()
125 if (!(mult & 0x8000)) in sh73a0_cpg_register_clock()
126 mult = 1; in sh73a0_cpg_register_clock()
128 mult = (mult & 0x3f) + 1; in sh73a0_cpg_register_clock()
154 mult, div); in sh73a0_cpg_register_clock()
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| D | clk-rz.c | 55 unsigned mult; in rz_cpg_register_clock() local
62 mult = cpg_mode ? (32 / 4) : 30; in rz_cpg_register_clock()
64 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1); in rz_cpg_register_clock()
82 mult = frqcr_tab[val]; in rz_cpg_register_clock()
83 return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3); in rz_cpg_register_clock()
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| D | clk-r8a73a4.c | 67 unsigned int mult = 1; in r8a73a4_cpg_register_clock() local
99 mult = ((value >> 24) & 0x7f) + 1; in r8a73a4_cpg_register_clock()
107 mult = ((value >> 24) & 0x7f) + 1; in r8a73a4_cpg_register_clock()
152 mult = ((value >> 24) & 0x7f) + 1; in r8a73a4_cpg_register_clock()
162 mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f); in r8a73a4_cpg_register_clock()
181 mult, div); in r8a73a4_cpg_register_clock()
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| D | clk-r8a7740.c | 69 unsigned int mult = 1; in r8a7740_cpg_register_clock() local
101 mult = ((value >> 24) & 0x7f) + 1; in r8a7740_cpg_register_clock()
105 mult = ((value >> 24) & 0x7f) + 1; in r8a7740_cpg_register_clock()
110 mult = ((value >> 24) & 0x3f) + 1; in r8a7740_cpg_register_clock()
137 mult, div); in r8a7740_cpg_register_clock()
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| /drivers/clk/mvebu/ |
| D | orion.c | 60 int *mult, int *div) in mv88f5181_get_clk_ratio() argument
65 *mult = 1; in mv88f5181_get_clk_ratio()
68 *mult = 1; in mv88f5181_get_clk_ratio()
71 *mult = 0; in mv88f5181_get_clk_ratio()
128 int *mult, int *div) in mv88f5182_get_clk_ratio() argument
133 *mult = 1; in mv88f5182_get_clk_ratio()
136 *mult = 1; in mv88f5182_get_clk_ratio()
139 *mult = 0; in mv88f5182_get_clk_ratio()
185 int *mult, int *div) in mv88f5281_get_clk_ratio() argument
190 *mult = 1; in mv88f5281_get_clk_ratio()
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| D | mv98dx3236.c | 118 void __iomem *sar, int id, int *mult, int *div) in mv98dx3236_get_clk_ratio() argument
126 *mult = mv98dx4251_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
129 *mult = mv98dx3236_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
135 *mult = mv98dx4251_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
138 *mult = mv98dx3236_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
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| D | armada-39x.c | 92 void __iomem *sar, int id, int *mult, int *div) in armada_39x_get_clk_ratio() argument
96 *mult = 1; in armada_39x_get_clk_ratio()
100 *mult = 1; in armada_39x_get_clk_ratio()
104 *mult = 1; in armada_39x_get_clk_ratio()
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| D | kirkwood.c | 127 void __iomem *sar, int id, int *mult, int *div) in kirkwood_get_clk_ratio() argument
133 *mult = kirkwood_cpu_l2_ratios[opt][0]; in kirkwood_get_clk_ratio()
141 *mult = kirkwood_cpu_ddr_ratios[opt][0]; in kirkwood_get_clk_ratio()
167 void __iomem *sar, int id, int *mult, int *div) in mv88f6180_get_clk_ratio() argument
173 *mult = 1; in mv88f6180_get_clk_ratio()
181 *mult = mv88f6180_cpu_ddr_ratios[opt][0]; in mv88f6180_get_clk_ratio()
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| /drivers/clk/sunxi/ |
| D | clk-sun4i-pll3.c | 24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local
48 mult = kzalloc(sizeof(*mult), GFP_KERNEL); in sun4i_a10_pll3_setup()
49 if (!mult) in sun4i_a10_pll3_setup()
52 mult->reg = reg; in sun4i_a10_pll3_setup()
53 mult->shift = SUN4I_A10_PLL3_DIV_SHIFT; in sun4i_a10_pll3_setup()
54 mult->width = SUN4I_A10_PLL3_DIV_WIDTH; in sun4i_a10_pll3_setup()
55 mult->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
60 &mult->hw, &clk_multiplier_ops, in sun4i_a10_pll3_setup()
80 kfree(mult); in sun4i_a10_pll3_setup()
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| D | clk-a10-pll2.c | 44 struct clk_multiplier *mult; in sun4i_pll2_setup() local
83 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); in sun4i_pll2_setup()
84 if (!mult) in sun4i_pll2_setup()
87 mult->reg = reg; in sun4i_pll2_setup()
88 mult->shift = SUN4I_PLL2_N_SHIFT; in sun4i_pll2_setup()
89 mult->width = 7; in sun4i_pll2_setup()
90 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | in sun4i_pll2_setup()
92 mult->lock = &sun4i_a10_pll2_lock; in sun4i_pll2_setup()
98 &mult->hw, &clk_multiplier_ops, in sun4i_pll2_setup()
168 kfree(mult); in sun4i_pll2_setup()
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| /drivers/clk/imx/ |
| D | clk-pllv4.c | 72 u32 mult, mfn, mfd; in clk_pllv4_recalc_rate() local
75 mult = readl_relaxed(pll->base + PLL_CFG_OFFSET); in clk_pllv4_recalc_rate()
76 mult &= BM_PLL_MULT; in clk_pllv4_recalc_rate()
77 mult >>= BP_PLL_MULT; in clk_pllv4_recalc_rate()
85 return (parent_rate * mult) + (u32)temp64; in clk_pllv4_recalc_rate()
135 static bool clk_pllv4_is_valid_mult(unsigned int mult) in clk_pllv4_is_valid_mult() argument
141 if (pllv4_mult_table[i] == mult) in clk_pllv4_is_valid_mult()
152 u32 val, mult, mfn, mfd = DEFAULT_MFD; in clk_pllv4_set_rate() local
155 mult = rate / parent_rate; in clk_pllv4_set_rate()
157 if (!clk_pllv4_is_valid_mult(mult)) in clk_pllv4_set_rate()
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| /drivers/iio/imu/inv_icm42600/ |
| D | inv_icm42600_timestamp.c | 50 ts->mult = default_period / INV_ICM42600_TIMESTAMP_PERIOD; in inv_icm42600_timestamp_init()
82 static bool inv_validate_period(uint32_t period, uint32_t mult) in inv_validate_period() argument
88 period_min = INV_ICM42600_TIMESTAMP_MIN_PERIOD(chip_period) * mult; in inv_validate_period()
89 period_max = INV_ICM42600_TIMESTAMP_MAX_PERIOD(chip_period) * mult; in inv_validate_period()
97 uint32_t mult, uint32_t period) in inv_compute_chip_period() argument
101 if (!inv_validate_period(period, mult)) in inv_compute_chip_period()
105 new_chip_period = period / mult; in inv_compute_chip_period()
136 ts->period = ts->mult * ts->chip_period.val; in inv_icm42600_timestamp_interrupt()
177 ts->mult = ts->new_mult; in inv_icm42600_timestamp_apply_odr()
179 ts->period = ts->mult * ts->chip_period.val; in inv_icm42600_timestamp_apply_odr()
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| /drivers/thermal/broadcom/ |
| D | brcmstb_thermal.c | 107 unsigned int mult; member
124 int mult = priv->temp_params->mult; in avs_tmon_code_to_temp() local
126 return (offset - (int)((code & AVS_TMON_TEMP_MASK) * mult)); in avs_tmon_code_to_temp()
139 int mult = priv->temp_params->mult; in avs_tmon_temp_to_code() local
148 return (u32)(DIV_ROUND_UP(offset - temp, mult)); in avs_tmon_temp_to_code()
150 return (u32)((offset - temp) / mult); in avs_tmon_temp_to_code()
297 .mult = 557,
308 .mult = 487,
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| /drivers/net/ethernet/mellanox/mlx4/ |
| D | en_clock.c | 124 u32 diff, mult; in mlx4_en_phc_adjfreq() local
134 mult = mdev->nominal_c_mult; in mlx4_en_phc_adjfreq()
135 adj = mult; in mlx4_en_phc_adjfreq()
141 mdev->cycles.mult = neg_adj ? mult - diff : mult + diff; in mlx4_en_phc_adjfreq()
281 mdev->cycles.mult = in mlx4_en_init_timestamp()
283 mdev->nominal_c_mult = mdev->cycles.mult; in mlx4_en_init_timestamp()
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| /drivers/net/ethernet/pensando/ionic/ |
| D | ionic_phc.c | 311 ctx->cmd.lif_setphc.mult = cpu_to_le32(phc->cc.mult); in ionic_setphc_cmd()
342 phc->cc.mult = adj; in ionic_phc_adjfine()
524 u64 delay, diff, mult; in ionic_lif_alloc_phc() local
544 phc->cc.mult = le32_to_cpu(ionic->ident.dev.hwstamp_mult); in ionic_lif_alloc_phc()
547 if (!phc->cc.mult) { in ionic_lif_alloc_phc()
550 phc->cc.mult); in ionic_lif_alloc_phc()
557 phc->cc.mask, phc->cc.mult, phc->cc.shift); in ionic_lif_alloc_phc()
567 diff = U64_MAX / phc->cc.mult / 2; in ionic_lif_alloc_phc()
571 diff = DIV_ROUND_UP(diff, phc->cc.mult); in ionic_lif_alloc_phc()
603 mult = U64_MAX / 2 / max(diff / 2, SCALED_PPM); in ionic_lif_alloc_phc()
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| /drivers/cpufreq/ |
| D | longhaul.c | 108 static unsigned int calc_speed(int mult) in calc_speed() argument
111 khz = (mult/10)*fsb; in calc_speed()
112 if (mult%10) in calc_speed()
249 int speed, mult; in longhaul_setstate() local
259 mult = mults[mults_index & 0x1f]; in longhaul_setstate()
260 if (mult == -1) in longhaul_setstate()
263 speed = calc_speed(mult); in longhaul_setstate()
275 fsb, mult/10, mult%10, print_speed(speed/1000)); in longhaul_setstate()
406 static int guess_fsb(int mult) in guess_fsb() argument
414 f_max = ((speeds[i] * mult) + 50) / 100; in guess_fsb()
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| /drivers/clk/davinci/ |
| D | pll.c | 120 u32 mult; in davinci_pll_recalc_rate() local
122 mult = readl(pll->base + PLLM) & pll->pllm_mask; in davinci_pll_recalc_rate()
123 rate *= mult + 1; in davinci_pll_recalc_rate()
136 u32 mult; in davinci_pll_determine_rate() local
143 mult = rate / parent_rate; in davinci_pll_determine_rate()
144 best_rate = parent_rate * mult; in davinci_pll_determine_rate()
151 if (mult < pll->pllm_min || mult > pll->pllm_max) in davinci_pll_determine_rate()
162 for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { in davinci_pll_determine_rate()
163 parent_rate = clk_hw_round_rate(parent, rate / mult); in davinci_pll_determine_rate()
164 r = parent_rate * mult; in davinci_pll_determine_rate()
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| /drivers/iio/common/scmi_sensors/ |
| D | scmi_iio.c | 134 u64 sec, mult, uHz, sf; in scmi_iio_set_odr_val() local
160 mult = scnprintf(buf, sizeof(buf), "%llu", sf) - 1; in scmi_iio_set_odr_val()
162 sec = int_pow(10, mult) * UHZ_PER_HZ; in scmi_iio_set_odr_val()
174 sensor_config |= FIELD_PREP(SCMI_SENS_CFG_UPDATE_EXP_MASK, -mult); in scmi_iio_set_odr_val()
251 int mult; in scmi_iio_get_odr_val() local
266 mult = SCMI_SENS_CFG_GET_UPDATE_EXP(sensor_config); in scmi_iio_get_odr_val()
267 if (mult < 0) { in scmi_iio_get_odr_val()
268 sensor_interval_mult = int_pow(10, abs(mult)); in scmi_iio_get_odr_val()
271 sensor_interval_mult = int_pow(10, mult); in scmi_iio_get_odr_val()
443 int mult; in scmi_iio_convert_interval_to_ns() local
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| /drivers/clk/x86/ |
| D | clk-cgu-pll.c | 25 lgm_pll_calc_rate(unsigned long prate, unsigned int mult, in lgm_pll_calc_rate() argument
31 crate = rate64 * mult; in lgm_pll_calc_rate()
43 unsigned int div, mult, frac; in lgm_pll_recalc_rate() local
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
52 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); in lgm_pll_recalc_rate()
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