Searched refs:next_fence (Results 1 – 6 of 6) sorted by relevance
610 u64 base_addr, next_fence; in hl_state_dump_print_engine_fences() local616 next_fence = sds->props[SP_NEXT_TPC]; in hl_state_dump_print_engine_fences()621 next_fence = sds->props[SP_NEXT_MME]; in hl_state_dump_print_engine_fences()626 next_fence = sds->props[SP_DMA_QUEUES_OFFSET]; in hl_state_dump_print_engine_fences()634 base_addr + next_fence * i + in hl_state_dump_print_engine_fences()636 base_addr + next_fence * i + in hl_state_dump_print_engine_fences()
1041 u8 next_fence) in handle_psv() argument1061 next_fence, MLX5_OPCODE_SET_PSV); in handle_psv()1073 u8 next_fence) in handle_reg_mr_integrity() argument1139 next_fence); in handle_reg_mr_integrity()1145 next_fence); in handle_reg_mr_integrity()1149 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; in handle_reg_mr_integrity()1159 u8 next_fence, int *num_sge) in handle_qpt_rc() argument1192 next_fence); in handle_qpt_rc()1296 u8 next_fence = 0; in mlx5_ib_post_send() local1340 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; in mlx5_ib_post_send()[all …]
486 u8 next_fence; member
121 u32 next_fence; member
1144 gpu->fence_context, ++gpu->next_fence); in etnaviv_gpu_fence_alloc()
473 struct vmw_fence_obj *fence, *next_fence; in __vmw_fences_update() local480 list_for_each_entry_safe(fence, next_fence, &fman->fence_list, head) { in __vmw_fences_update()