| /drivers/mailbox/ |
| D | rockchip-mailbox.c | 31 int num_chans; member
84 writel_relaxed((1 << mb->mbox.num_chans) - 1, in rockchip_mbox_startup()
113 for (idx = 0; idx < mb->mbox.num_chans; idx++) { in rockchip_mbox_irq()
131 for (idx = 0; idx < mb->mbox.num_chans; idx++) { in rockchip_mbox_isr()
155 .num_chans = 4,
182 mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, in rockchip_mbox_probe()
187 mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans, in rockchip_mbox_probe()
195 mb->mbox.num_chans = drv_data->num_chans; in rockchip_mbox_probe()
208 mb->buf_size = (size_t)resource_size(res) / (drv_data->num_chans * 2); in rockchip_mbox_probe()
224 for (i = 0; i < mb->mbox.num_chans; i++) { in rockchip_mbox_probe()
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| D | arm_mhu_db.c | 66 for (i = 0; i < mbox->num_chans; i++) { in mhu_db_mbox_to_channel()
172 for (i = 0; i < mbox->num_chans; i++) in mhu_db_shutdown()
176 if (mbox->num_chans == i) { in mhu_db_shutdown()
214 for (i = 0; i < mbox->num_chans; i++) in mhu_db_mbox_xlate()
218 if (mbox->num_chans == i) { in mhu_db_mbox_xlate()
291 mhu->mbox.num_chans = max_chans; in mhu_db_probe()
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| D | pcc.c | 85 if (id < 0 || id >= pcc_mbox_ctrl.num_chans) in get_pcc_channel()
294 if (id >= pcc_mbox_ctrl.num_chans) { in pcc_mbox_free_channel()
334 if (id >= pcc_mbox_ctrl.num_chans) { in pcc_send_data()
527 pcc_mbox_ctrl.num_chans = count; in acpi_pcc_probe()
529 pr_info("Detected %d PCC Subspaces\n", pcc_mbox_ctrl.num_chans); in acpi_pcc_probe()
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| D | mailbox-sti.c | 104 for (i = 0; i < mbox->num_chans; i++) { in sti_mbox_to_channel()
306 for (i = 0; i < mbox->num_chans; i++) in sti_mbox_shutdown_chan()
310 if (mbox->num_chans == i) { in sti_mbox_shutdown_chan()
340 for (i = 0; i < mbox->num_chans; i++) { in sti_mbox_xlate()
459 mbox->num_chans = STI_MBOX_CHAN_MAX; in sti_mbox_probe()
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| D | mailbox.c | 125 for (i = 0; i < mbox->num_chans; i++) { in txdone_hrtimer()
472 if (ind >= mbox->num_chans) in of_mbox_index_xlate()
489 if (!mbox || !mbox->dev || !mbox->ops || !mbox->num_chans) in mbox_controller_register()
512 for (i = 0; i < mbox->num_chans; i++) { in mbox_controller_register()
547 for (i = 0; i < mbox->num_chans; i++) in mbox_controller_unregister()
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| D | tegra-hsp.c | 183 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) { in tegra_hsp_doorbell_irq()
318 if (db->master >= chan->mbox->num_chans) { in tegra_hsp_doorbell_startup()
530 for (i = 0; i < mbox->num_chans; i++) { in tegra_hsp_db_xlate()
711 hsp->mbox_db.num_chans = 32; in tegra_hsp_probe()
715 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans, in tegra_hsp_probe()
739 hsp->mbox_sm.num_chans = hsp->num_sm; in tegra_hsp_probe()
743 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans, in tegra_hsp_probe()
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| D | stm32-ipcc.c | 297 ipcc->controller.num_chans = ipcc->n_chans; in stm32_ipcc_probe()
298 ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans, in stm32_ipcc_probe()
306 for (i = 0; i < ipcc->controller.num_chans; i++) in stm32_ipcc_probe()
320 ipcc->controller.num_chans, ipcc->proc_id); in stm32_ipcc_probe()
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| D | imx-mailbox.c | 430 if (chan >= mbox->num_chans) { in imx_mu_scu_xlate()
452 if (chan >= mbox->num_chans) { in imx_mu_xlate()
475 priv->mbox.num_chans = IMX_MU_CHANS; in imx_mu_init_generic()
501 priv->mbox.num_chans = IMX_MU_SCU_CHANS; in imx_mu_init_scu()
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| D | arm_mhuv2.c | 651 while (i < mhu->mbox.num_chans) { in get_irq_chan_stat_rx()
867 mhu->mbox.num_chans = channels; in mhuv2_verify_protocol()
879 chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*chans), GFP_KERNEL); in mhuv2_allocate_channels()
925 BUG_ON(chans - mbox->chans != mbox->num_chans); in mhuv2_allocate_channels()
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| D | arm_mhu.c | 137 mhu->mbox.num_chans = MHU_CHANS; in mhu_probe()
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| D | platform_mhu.c | 150 mhu->mbox.num_chans = MHU_CHANS; in platform_mhu_probe()
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| D | bcm2835-mailbox.c | 168 mbox->controller.num_chans = 1; in bcm2835_mbox_probe()
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| D | qcom-apcs-ipc-mailbox.c | 128 apcs->mbox.num_chans = ARRAY_SIZE(apcs->mbox_chans); in qcom_apcs_ipc_probe()
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| D | armada-37xx-rwtm-mailbox.c | 171 mbox->controller.num_chans = 1; in armada_37xx_mbox_probe()
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| D | mailbox-xgene-slimpro.c | 212 ctx->mb_ctrl.num_chans = i; in slimpro_mbox_probe()
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| D | hi3660-mailbox.c | 259 mbox->controller.num_chans = MBOX_CHAN_MAX; in hi3660_mbox_probe()
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| D | qcom-ipcc.c | 202 mbox->num_chans = IPCC_MBOX_MAX_CHAN; in qcom_ipcc_setup_mbox()
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| D | mailbox-mpfs.c | 254 mbox->controller.num_chans = 1; in mpfs_mbox_probe()
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| /drivers/input/joystick/ |
| D | adc-joystick.c | 28 int num_chans; member
41 for (i = 0; i < joy->num_chans; ++i) { in adc_joystick_handle()
119 if (num_axes != joy->num_chans) { in adc_joystick_set_axes()
121 num_axes, joy->num_chans); in adc_joystick_set_axes()
207 joy->num_chans = i; in adc_joystick_probe()
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| /drivers/edac/ |
| D | cell_edac.c | 175 int rc, chanmask, num_chans; in cell_edac_probe() local
200 num_chans = chanmask == 3 ? 2 : 1; in cell_edac_probe()
206 layers[1].size = num_chans; in cell_edac_probe()
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| /drivers/firmware/ |
| D | arm_scpi.c | 249 int num_chans; member
488 scpi_info->num_chans; in scpi_send_message()
859 for (i = 0; i < info->num_chans; i++) in scpi_free_channels()
940 for (; scpi_drvinfo->num_chans < count; scpi_drvinfo->num_chans++) { in scpi_probe()
942 int idx = scpi_drvinfo->num_chans; in scpi_probe()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_socbb.h | 69 uint32_t num_chans; member
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 1195 bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()
1197 bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans * in dcn303_get_optimal_dcfclk_fclk_for_uclk()
1227 if (dc->ctx->dc_bios->vram_info.num_chans) in dcn303_update_bw_bounding_box()
1228 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn303_update_bw_bounding_box()
1349 if (dcn3_03_soc.num_chans <= 4) { in dcn303_update_bw_bounding_box()
1458 dc->ctx->dc_bios->vram_info.num_chans * in dcn303_resource_construct()
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| /drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| D | p2p.c | 643 static s32 brcmf_p2p_escan(struct brcmf_p2p_info *p2p, u32 num_chans, in brcmf_p2p_escan() argument
659 memsize += num_chans * sizeof(__le16); in brcmf_p2p_escan()
717 if (num_chans == SOCIAL_CHAN_CNT || num_chans == (SOCIAL_CHAN_CNT + 1)) in brcmf_p2p_escan()
719 else if (num_chans == AF_PEER_SEARCH_CNT) in brcmf_p2p_escan()
727 if (num_chans == 1) { in brcmf_p2p_escan()
744 sparams->channel_num = cpu_to_le32(num_chans & in brcmf_p2p_escan()
746 for (i = 0; i < num_chans; i++) in brcmf_p2p_escan()
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 1266 bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
1268 bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
1297 if (dc->ctx->dc_bios->vram_info.num_chans) in dcn302_update_bw_bounding_box()
1298 dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn302_update_bw_bounding_box()
1516 …_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; in dcn302_resource_construct()
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