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Searched refs:offsets (Results 1 – 25 of 147) sorted by relevance

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/drivers/staging/media/atomisp/pci/css_2401_system/hive/
Dia_css_isp_configs.c38 if (binary->info->mem_offsets.offsets.config) { in ia_css_configure_iterator()
39 size = binary->info->mem_offsets.offsets.config->dmem.iterator.size; in ia_css_configure_iterator()
40 offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; in ia_css_configure_iterator()
66 if (binary->info->mem_offsets.offsets.config) { in ia_css_configure_copy_output()
67 size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size; in ia_css_configure_copy_output()
68 offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; in ia_css_configure_copy_output()
94 if (binary->info->mem_offsets.offsets.config) { in ia_css_configure_crop()
95 size = binary->info->mem_offsets.offsets.config->dmem.crop.size; in ia_css_configure_crop()
96 offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; in ia_css_configure_crop()
122 if (binary->info->mem_offsets.offsets.config) { in ia_css_configure_fpn()
[all …]
Dia_css_isp_states.c33 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.aa.size; in ia_css_initialize_aa_state()
34 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset; in ia_css_initialize_aa_state()
54 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr.size; in ia_css_initialize_cnr_state()
56 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset; in ia_css_initialize_cnr_state()
78 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size; in ia_css_initialize_cnr2_state()
80 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset; in ia_css_initialize_cnr2_state()
102 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.dp.size; in ia_css_initialize_dp_state()
104 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset; in ia_css_initialize_dp_state()
126 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.de.size; in ia_css_initialize_de_state()
128 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.de.offset; in ia_css_initialize_de_state()
[all …]
Dia_css_isp_params.c76 stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; in ia_css_process_aa()
78 stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; in ia_css_process_aa()
99 stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; in ia_css_process_anr()
102 stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; in ia_css_process_anr()
134 stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size; in ia_css_process_anr2()
137 stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset; in ia_css_process_anr2()
169 stage->binary->info->mem_offsets.offsets.param->dmem.bh.size; in ia_css_process_bh()
172 stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset; in ia_css_process_bh()
190 stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size; in ia_css_process_bh()
216 stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size; in ia_css_process_cnr()
[all …]
/drivers/staging/media/atomisp/pci/css_2400_system/hive/
Dia_css_isp_configs.c38 if (binary->info->mem_offsets.offsets.config) { in ia_css_configure_iterator()
39 size = binary->info->mem_offsets.offsets.config->dmem.iterator.size; in ia_css_configure_iterator()
40 offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; in ia_css_configure_iterator()
66 if (binary->info->mem_offsets.offsets.config) { in ia_css_configure_copy_output()
67 size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size; in ia_css_configure_copy_output()
68 offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; in ia_css_configure_copy_output()
94 if (binary->info->mem_offsets.offsets.config) { in ia_css_configure_crop()
95 size = binary->info->mem_offsets.offsets.config->dmem.crop.size; in ia_css_configure_crop()
96 offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; in ia_css_configure_crop()
122 if (binary->info->mem_offsets.offsets.config) { in ia_css_configure_fpn()
[all …]
Dia_css_isp_states.c32 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.aa.size; in ia_css_initialize_aa_state()
34 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset; in ia_css_initialize_aa_state()
54 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr.size; in ia_css_initialize_cnr_state()
56 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset; in ia_css_initialize_cnr_state()
78 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size; in ia_css_initialize_cnr2_state()
80 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset; in ia_css_initialize_cnr2_state()
102 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.dp.size; in ia_css_initialize_dp_state()
104 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset; in ia_css_initialize_dp_state()
126 unsigned int size = binary->info->mem_offsets.offsets.state->vmem.de.size; in ia_css_initialize_de_state()
128 unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.de.offset; in ia_css_initialize_de_state()
[all …]
Dia_css_isp_params.c75 stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; in ia_css_process_aa()
77 stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; in ia_css_process_aa()
101 stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; in ia_css_process_anr()
104 stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; in ia_css_process_anr()
136 stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size; in ia_css_process_anr2()
139 stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset; in ia_css_process_anr2()
171 stage->binary->info->mem_offsets.offsets.param->dmem.bh.size; in ia_css_process_bh()
174 stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset; in ia_css_process_bh()
192 stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size; in ia_css_process_bh()
218 stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size; in ia_css_process_cnr()
[all …]
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_timing_generator.c43 generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
46 generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
93 tg110->offsets.crtc); in dce120_timing_generator_is_in_vertical_blank()
176 tg110->offsets.crtc); in dce120_timing_generator_get_vblank_counter()
192 tg110->offsets.crtc); in dce120_timing_generator_get_crtc_position()
203 tg110->offsets.crtc); in dce120_timing_generator_get_crtc_position()
253 tg110->offsets.crtc); in dce120_timing_generator_setup_global_swap_lock()
261 dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0); in dce120_timing_generator_setup_global_swap_lock()
315 tg110->offsets.crtc); in dce120_timing_generator_enable_reset_trigger()
377 tg110->offsets.crtc); in dce120_timing_generator_did_triggered_reset_occur()
[all …]
/drivers/media/platform/atmel/
Datmel-sama5d2-isc.c195 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama5d2_config_csc()
197 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama5d2_config_csc()
199 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama5d2_config_csc()
201 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama5d2_config_csc()
203 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama5d2_config_csc()
205 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama5d2_config_csc()
213 regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, in isc_sama5d2_config_cbc()
215 regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, in isc_sama5d2_config_cbc()
275 regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, in isc_sama5d2_config_rlp()
439 isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; in atmel_isc_probe()
[all …]
Datmel-sama7g5-isc.c212 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama7g5_config_csc()
214 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama7g5_config_csc()
216 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama7g5_config_csc()
218 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama7g5_config_csc()
220 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama7g5_config_csc()
222 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama7g5_config_csc()
231 regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness); in isc_sama7g5_config_cbc()
232 regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast); in isc_sama7g5_config_cbc()
286 regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, in isc_sama7g5_config_rlp()
432 isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; in microchip_xisc_probe()
[all …]
/drivers/mtd/tests/
Dstresstest.c36 static int *offsets; variable
96 offs = offsets[eb]; in do_write()
101 offs = offsets[eb] = 0; in do_write()
112 offsets[eb + 1] = 0; in do_write()
121 offsets[eb++] = mtd->erasesize; in do_write()
124 offsets[eb] = offs; in do_write()
190 offsets = kmalloc_array(ebcnt, sizeof(int), GFP_KERNEL); in mtd_stresstest_init()
191 if (!readbuf || !writebuf || !offsets) in mtd_stresstest_init()
194 offsets[i] = mtd->erasesize; in mtd_stresstest_init()
220 kfree(offsets); in mtd_stresstest_init()
/drivers/gpio/
Dgpio-msc313.c195 const unsigned int *offsets; member
202 .offsets = _chip##_offsets, \
235 u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]); in msc313_gpio_set()
242 writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]); in msc313_gpio_set()
249 return readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]) & MSC313_GPIO_IN; in msc313_gpio_get()
255 u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]); in msc313_gpio_direction_input()
258 writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]); in msc313_gpio_direction_input()
266 u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]); in msc313_gpio_direction_output()
273 writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]); in msc313_gpio_direction_output()
322 unsigned int offset = priv->gpio_data->offsets[child]; in msc313e_gpio_child_to_parent_hwirq()
[all …]
/drivers/media/platform/rockchip/rga/
Drga-hw.c49 struct rga_corners_addr_offset offsets; in rga_get_addr_offset() local
54 lt = &offsets.left_top; in rga_get_addr_offset()
55 lb = &offsets.left_bottom; in rga_get_addr_offset()
56 rt = &offsets.right_top; in rga_get_addr_offset()
57 rb = &offsets.right_bottom; in rga_get_addr_offset()
82 return offsets; in rga_get_addr_offset()
87 * offsets, u32 rotate_mode, in rga_lookup_draw_pos()
105 if (!offsets) in rga_lookup_draw_pos()
110 return &offsets->left_top; in rga_lookup_draw_pos()
112 return &offsets->left_bottom; in rga_lookup_draw_pos()
[all …]
/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/bayer_io_ls/
Dia_css_bayer_io.host.c42 if (binary->info->mem_offsets.offsets.param) { in ia_css_bayer_io_config()
43 size_get = binary->info->mem_offsets.offsets.param->dmem.get.size; in ia_css_bayer_io_config()
44 offset = binary->info->mem_offsets.offsets.param->dmem.get.offset; in ia_css_bayer_io_config()
68 if (binary->info->mem_offsets.offsets.param) { in ia_css_bayer_io_config()
69 size_put = binary->info->mem_offsets.offsets.param->dmem.put.size; in ia_css_bayer_io_config()
70 offset = binary->info->mem_offsets.offsets.param->dmem.put.offset; in ia_css_bayer_io_config()
/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/yuv444_io_ls/
Dia_css_yuv444_io.host.c42 if (binary->info->mem_offsets.offsets.param) { in ia_css_yuv444_io_config()
43 size_get = binary->info->mem_offsets.offsets.param->dmem.get.size; in ia_css_yuv444_io_config()
44 offset = binary->info->mem_offsets.offsets.param->dmem.get.offset; in ia_css_yuv444_io_config()
68 if (binary->info->mem_offsets.offsets.param) { in ia_css_yuv444_io_config()
69 size_put = binary->info->mem_offsets.offsets.param->dmem.put.size; in ia_css_yuv444_io_config()
70 offset = binary->info->mem_offsets.offsets.param->dmem.put.offset; in ia_css_yuv444_io_config()
/drivers/memory/
DMakefile37 $(obj)/ti-emif-sram-pm.o: $(obj)/ti-emif-asm-offsets.h
39 $(obj)/ti-emif-asm-offsets.h: $(obj)/emif-asm-offsets.s FORCE
40 $(call filechk,offsets,__TI_EMIF_ASM_OFFSETS_H__)
42 targets += emif-asm-offsets.s
43 clean-files += ti-emif-asm-offsets.h
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_timing_generator.c83 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
84 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
85 #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
91 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
229 const struct dce110_timing_generator_offsets *offsets) in dce80_timing_generator_construct() argument
233 tg110->offsets = *offsets; in dce80_timing_generator_construct()
/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_execbuffer.c22 const unsigned int offsets[] = { 8, 3, 0 }; in __igt_gpu_reloc() local
44 err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); in __igt_gpu_reloc()
49 err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); in __igt_gpu_reloc()
61 err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); in __igt_gpu_reloc()
82 for (i = 0; i < ARRAY_SIZE(offsets); i++) { in __igt_gpu_reloc()
83 u64 reloc = read_reloc(map, offsets[i], mask); in __igt_gpu_reloc()
87 eb->engine->name, i, offsets[i], reloc, i); in __igt_gpu_reloc()
Di915_gem_coherency.c316 u32 *offsets, *values; in igt_gem_coherency() local
328 offsets = kmalloc_array(ncachelines, 2*sizeof(u32), GFP_KERNEL); in igt_gem_coherency()
329 if (!offsets) in igt_gem_coherency()
332 offsets[count] = count * 64 + 4 * (count % 16); in igt_gem_coherency()
334 values = offsets + ncachelines; in igt_gem_coherency()
372 i915_random_reorder(offsets, ncachelines, &prng); in igt_gem_coherency()
377 err = over->set(&ctx, offsets[n], ~values[n]); in igt_gem_coherency()
386 err = write->set(&ctx, offsets[n], values[n]); in igt_gem_coherency()
397 err = read->get(&ctx, offsets[n], &found); in igt_gem_coherency()
409 ~values[n], offsets[n]); in igt_gem_coherency()
[all …]
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_timing_generator.c83 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
84 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
85 #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
91 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
247 const struct dce110_timing_generator_offsets *offsets) in dce60_timing_generator_construct() argument
251 tg110->offsets = *offsets; in dce60_timing_generator_construct()
/drivers/bus/
Dti-sysc.c132 int offsets[SYSC_MAX_REGS]; member
167 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_write()
168 offset == ddata->offsets[SYSC_REVISION]) { in sysc_write()
188 if (ddata->offsets[SYSC_REVISION] >= 0 && in sysc_read()
189 offset == ddata->offsets[SYSC_REVISION]) { in sysc_read()
208 int offset = ddata->offsets[SYSC_REVISION]; in sysc_read_revision()
218 int offset = ddata->offsets[SYSC_SYSCONFIG]; in sysc_read_sysconfig()
228 int offset = ddata->offsets[SYSC_SYSSTATUS]; in sysc_read_sysstatus()
297 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; in sysc_wait_softreset()
844 ddata->offsets[reg] = -ENODEV; in sysc_parse_one()
[all …]
/drivers/memory/tegra/
Dtegra210-emc-cc-r21021.c1006 const u16 *offsets = emc->offsets->burst; in tegra210_emc_r21021_set_clock() local
1009 if (!offsets[i]) in tegra210_emc_r21021_set_clock()
1013 offset = offsets[i]; in tegra210_emc_r21021_set_clock()
1086 emc->offsets->burst_per_channel; in tegra210_emc_r21021_set_clock()
1120 emc->offsets->vref_per_channel; in tegra210_emc_r21021_set_clock()
1138 const u16 *offsets = emc->offsets->trim; in tegra210_emc_r21021_set_clock() local
1140 if (!offsets[i]) in tegra210_emc_r21021_set_clock()
1144 (offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 || in tegra210_emc_r21021_set_clock()
1145 offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 || in tegra210_emc_r21021_set_clock()
1146 offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 || in tegra210_emc_r21021_set_clock()
[all …]
/drivers/infiniband/hw/mlx5/
Dcounters.c207 val = *(__be32 *)((void *)out + cnts->offsets[i]); in mlx5_ib_query_q_counters()
238 cnts->offsets[i + offset])); in mlx5_ib_query_ext_ppcnt_counters()
286 cnts->offsets + in mlx5_ib_get_hw_stats()
377 size_t *offsets) in mlx5_ib_fill_counters() argument
384 offsets[j] = basic_q_cnts[i].offset; in mlx5_ib_fill_counters()
390 offsets[j] = out_of_seq_q_cnts[i].offset; in mlx5_ib_fill_counters()
397 offsets[j] = retrans_q_cnts[i].offset; in mlx5_ib_fill_counters()
404 offsets[j] = extended_err_cnts[i].offset; in mlx5_ib_fill_counters()
411 offsets[j] = roce_accl_cnts[i].offset; in mlx5_ib_fill_counters()
418 offsets[j] = cong_cnts[i].offset; in mlx5_ib_fill_counters()
[all …]
/drivers/gpu/drm/
Ddrm_client_modeset.c260 struct drm_client_offset *offsets, in drm_client_target_cloned() argument
344 struct drm_client_offset *offsets, in drm_client_get_tile_offsets() argument
368 offsets[idx].x = hoffset; in drm_client_get_tile_offsets()
369 offsets[idx].y = voffset; in drm_client_get_tile_offsets()
377 struct drm_client_offset *offsets, in drm_client_target_preferred() argument
424 drm_client_get_tile_offsets(connectors, connector_count, modes, offsets, i, in drm_client_target_preferred()
569 struct drm_client_offset *offsets, in drm_client_firmware_config() argument
776 struct drm_client_offset *offsets; in drm_client_modeset_probe() local
811 offsets = kcalloc(connector_count, sizeof(*offsets), GFP_KERNEL); in drm_client_modeset_probe()
813 if (!crtcs || !modes || !enabled || !offsets) { in drm_client_modeset_probe()
[all …]
/drivers/gpu/drm/vc4/
Dvc4_plane.c356 vc4_state->offsets[i] = bo->paddr + fb->offsets[i]; in vc4_plane_setup_clipping_and_scaling()
685 vc4_state->offsets[i] += src_y / in vc4_plane_mode_set()
689 vc4_state->offsets[i] += vc4_state->src_x / in vc4_plane_mode_set()
746 vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift); in vc4_plane_mode_set()
747 vc4_state->offsets[0] += subtile_y << 8; in vc4_plane_mode_set()
748 vc4_state->offsets[0] += utile_y << 4; in vc4_plane_mode_set()
753 vc4_state->offsets[0] += (tiles_w - tiles_l) << in vc4_plane_mode_set()
755 vc4_state->offsets[0] -= (1 + !tile_y) << 10; in vc4_plane_mode_set()
757 vc4_state->offsets[0] += tiles_l << tile_size_shift; in vc4_plane_mode_set()
758 vc4_state->offsets[0] += tile_y << 10; in vc4_plane_mode_set()
[all …]
/drivers/gpu/drm/selftests/
Dtest-drm_framebuffer.c76 .handles = { 1, 0, 0 }, .offsets = { UINT_MAX - 1, 0, 0 }, .pitches = { 4 * MAX_WIDTH, 0, 0 },
81 .handles = { 1, 0, 0 }, .offsets = { UINT_MAX / 2, 0, 0 }, .pitches = { 4 * MAX_WIDTH, 0, 0 },
86 .handles = { 1, 0, 0 }, .offsets = { UINT_MAX / 2, 0, 0 },
92 .handles = { 1, 0, 0 }, .offsets = { UINT_MAX / 2, 0, 0 }, .pitches = { 4 * MAX_WIDTH, 0, 0 },
98 .handles = { 1, 0, 0 }, .offsets = { UINT_MAX / 2, 0, 0 },
105 .handles = { 1, 0, 0 }, .offsets = { UINT_MAX / 2, 0, 0 },
206 .handles = { 1, 1, 1 }, .offsets = { MAX_WIDTH, MAX_WIDTH + MAX_WIDTH * MAX_HEIGHT,
281 .handles = { 1, 0, 0 }, .offsets = { 0, 0, 3 },

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