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Searched refs:out_8 (Results 1 – 25 of 56) sorted by relevance

123

/drivers/i2c/busses/
Di2c-ibm_iic.c126 out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0); in iic_interrupt_mode()
139 out_8(&iic->lmadr, 0); in iic_dev_init()
140 out_8(&iic->hmadr, 0); in iic_dev_init()
143 out_8(&iic->lsadr, 0); in iic_dev_init()
144 out_8(&iic->hsadr, 0); in iic_dev_init()
147 out_8(&iic->sts, STS_SCMP | STS_IRQA); in iic_dev_init()
148 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA in iic_dev_init()
152 out_8(&iic->clkdiv, dev->clckdiv); in iic_dev_init()
155 out_8(&iic->xfrcnt, 0); in iic_dev_init()
158 out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC in iic_dev_init()
[all …]
Di2c-cpm.c129 out_8(&i2c_reg->i2cer, i); in cpm_i2c_interrupt()
147 out_8(&i2c_ram->tfcr, I2C_EB); in cpm_reset_i2c_params()
148 out_8(&i2c_ram->rfcr, I2C_EB); in cpm_reset_i2c_params()
150 out_8(&i2c_ram->tfcr, I2C_EB_CPM2); in cpm_reset_i2c_params()
151 out_8(&i2c_ram->rfcr, I2C_EB_CPM2); in cpm_reset_i2c_params()
177 out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */ in cpm_i2c_force_close()
178 out_8(&i2c_reg->i2cer, 0xff); in cpm_i2c_force_close()
324 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); in cpm_i2c_xfer()
338 out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB); in cpm_i2c_xfer()
339 out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */ in cpm_i2c_xfer()
[all …]
/drivers/macintosh/
Dmacio-adb.c113 out_8(&adb->ctrl.r, 0); in macio_init()
114 out_8(&adb->intr.r, 0); in macio_init()
115 out_8(&adb->error.r, 0); in macio_init()
116 out_8(&adb->active_hi.r, 0xff); /* for now, set all devices active */ in macio_init()
117 out_8(&adb->active_lo.r, 0xff); in macio_init()
118 out_8(&adb->autopoll.r, APE); in macio_init()
126 out_8(&adb->intr_enb.r, DFB | TAG); in macio_init()
138 out_8(&adb->active_hi.r, devs >> 8); in macio_adb_autopoll()
139 out_8(&adb->active_lo.r, devs); in macio_adb_autopoll()
140 out_8(&adb->autopoll.r, devs? APE: 0); in macio_adb_autopoll()
[all …]
Dvia-cuda.c108 out_8(&via[B], in_8(&via[B]) | TIP); in assert_TIP()
110 out_8(&via[B], in_8(&via[B]) & ~TIP); in assert_TIP()
117 out_8(&via[B], in_8(&via[B]) | TIP | TACK); in assert_TIP_and_TACK()
119 out_8(&via[B], in_8(&via[B]) & ~(TIP | TACK)); in assert_TIP_and_TACK()
126 out_8(&via[B], in_8(&via[B]) | TACK); in assert_TACK()
128 out_8(&via[B], in_8(&via[B]) & ~TACK); in assert_TACK()
133 out_8(&via[B], in_8(&via[B]) ^ TACK); in toggle_TACK()
140 out_8(&via[B], in_8(&via[B]) & ~TACK); in negate_TACK()
142 out_8(&via[B], in_8(&via[B]) | TACK); in negate_TACK()
149 out_8(&via[B], in_8(&via[B]) & ~(TIP | TACK)); in negate_TIP_and_TACK()
[all …]
Dvia-pmu.c362 out_8(&via1[IER], IER_CLR | 0x7f); /* disable all intrs */ in find_via_pmu()
363 out_8(&via1[IFR], 0x7f); /* clear IFR */ in find_via_pmu()
475 out_8(&via1[IER], IER_SET | SR_INT | CB1_INT); in via_pmu_start()
586 out_8(&via2[B], in_8(&via2[B]) | TREQ); in init_pmu()
587 out_8(&via2[DIRB], (in_8(&via2[DIRB]) | TREQ) & ~TACK); in init_pmu()
1209 out_8(&via1[ACR], in_8(&via1[ACR]) | SR_OUT | SR_EXT); in send_byte()
1210 out_8(&via1[SR], x); in send_byte()
1211 out_8(&via2[B], in_8(&via2[B]) & ~TREQ); /* assert TREQ */ in send_byte()
1218 out_8(&via1[ACR], (in_8(&via1[ACR]) & ~SR_OUT) | SR_EXT); in recv_byte()
1220 out_8(&via2[B], in_8(&via2[B]) & ~TREQ); in recv_byte()
[all …]
/drivers/scsi/
Dmesh.c368 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_init()
369 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_init()
370 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_init()
373 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_init()
374 out_8(&mr->source_id, ms->host->this_id); in mesh_init()
375 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_init()
376 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
382 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_init()
385 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_init()
393 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */ in mesh_init()
[all …]
/drivers/rtc/
Drtc-mpc5121.c92 out_8(&regs->second_set, tm->tm_sec); in mpc5121_rtc_update_smh()
93 out_8(&regs->minute_set, tm->tm_min); in mpc5121_rtc_update_smh()
94 out_8(&regs->hour_set, tm->tm_hour); in mpc5121_rtc_update_smh()
97 out_8(&regs->set_time, 0x1); in mpc5121_rtc_update_smh()
98 out_8(&regs->set_time, 0x3); in mpc5121_rtc_update_smh()
99 out_8(&regs->set_time, 0x1); in mpc5121_rtc_update_smh()
100 out_8(&regs->set_time, 0x0); in mpc5121_rtc_update_smh()
182 out_8(&regs->month_set, tm->tm_mon + 1); in mpc5200_rtc_set_time()
183 out_8(&regs->weekday_set, tm->tm_wday ? tm->tm_wday : 7); in mpc5200_rtc_set_time()
184 out_8(&regs->date_set, tm->tm_mday); in mpc5200_rtc_set_time()
[all …]
/drivers/video/fbdev/
Dhpfb.c121 out_8(fb_regs + TC_NBLANK, (blank ? 0x00 : fb_bitmask)); in hpfb_blank()
132 out_8(fb_regs + TC_FBEN, fb_bitmask); in topcat_blit()
134 out_8(fb_regs + TC_WEN, fb_bitmask); in topcat_blit()
135 out_8(fb_regs + WMRR, rr); in topcat_blit()
143 out_8(fb_regs + WMOVE, fb_bitmask); in topcat_blit()
161 out_8(fb_regs + TC_WEN, fb_bitmask & clr); in hpfb_fillrect()
162 out_8(fb_regs + WMRR, (region->rop == ROP_COPY ? RR_SET : RR_INVERT)); in hpfb_fillrect()
165 out_8(fb_regs + TC_WEN, fb_bitmask & ~clr); in hpfb_fillrect()
166 out_8(fb_regs + WMRR, (region->rop == ROP_COPY ? RR_CLEAR : RR_NOOP)); in hpfb_fillrect()
180 out_8(fb_regs + TC_WEN, fb_bitmask); in hpfb_sync()
[all …]
Ddnfb.c142 out_8(AP_CONTROL_3A, 0x0); in dnfb_blank()
144 out_8(AP_CONTROL_3A, 0x1); in dnfb_blank()
169 out_8(AP_CONTROL_0, in dnfb_copyarea()
179 out_8(AP_CONTROL_0, in dnfb_copyarea()
188 out_8(AP_CONTROL_3A, 0xc | (dest >> 16)); in dnfb_copyarea()
196 out_8(AP_WRITE_ENABLE, start_mask); in dnfb_copyarea()
200 out_8(AP_WRITE_ENABLE, 0); in dnfb_copyarea()
208 out_8(AP_WRITE_ENABLE, start_mask); in dnfb_copyarea()
213 out_8(AP_WRITE_ENABLE, start_mask | end_mask); in dnfb_copyarea()
221 out_8(AP_CONTROL_0, NORMAL_MODE); in dnfb_copyarea()
[all …]
Dvalkyriefb.c143 out_8(&valkyrie_regs->status.r, 0); in valkyriefb_set_par()
148 out_8(&valkyrie_regs->mode.r, init->mode | 0x80); in valkyriefb_set_par()
149 out_8(&valkyrie_regs->depth.r, par->cmode + 3); in valkyriefb_set_par()
154 out_8(&valkyrie_regs->mode.r, init->mode); in valkyriefb_set_par()
199 out_8(&p->valkyrie_regs->mode.r, init->mode); in valkyriefb_blank()
210 out_8(&p->valkyrie_regs->mode.r, init->mode | 0x40); in valkyriefb_blank()
213 out_8(&p->valkyrie_regs->mode.r, 0x66); in valkyriefb_blank()
234 out_8(&p->cmap_regs->addr, regno); in valkyriefb_setcolreg()
237 out_8(&cmap_regs->lut, red); in valkyriefb_setcolreg()
238 out_8(&cmap_regs->lut, green); in valkyriefb_setcolreg()
[all …]
Dcontrolfb.c63 #undef out_8
67 #define out_8(addr, val) (void)(val) macro
170 out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */ in controlfb_setcolreg()
171 out_8(&p->cmap_regs->lut, r); /* send one color channel at */ in controlfb_setcolreg()
172 out_8(&p->cmap_regs->lut, g); /* a time... */ in controlfb_setcolreg()
173 out_8(&p->cmap_regs->lut, b); in controlfb_setcolreg()
227 out_8(&p->cmap_regs->addr, (a)); \
228 out_8(&p->cmap_regs->dat, (d))
301 out_8(&p->frame_buffer[0x600000], 0xb3); in find_vram_size()
302 out_8(&p->frame_buffer[0x600001], 0x71); in find_vram_size()
[all …]
Dplatinumfb.c199 out_8(&cmap_regs->addr, regno); /* tell clut what addr to fill */ in platinumfb_setcolreg()
200 out_8(&cmap_regs->lut, red); /* send one color channel at */ in platinumfb_setcolreg()
201 out_8(&cmap_regs->lut, green); /* a time... */ in platinumfb_setcolreg()
202 out_8(&cmap_regs->lut, blue); in platinumfb_setcolreg()
234 out_8(&cmap_regs->addr, (a+32)); \
235 out_8(&cmap_regs->d2, (d)); \
246 out_8(&cmap_regs->addr,3+32); in set_platinum_clock()
610 out_8(&pinfo->cmap_regs->addr, 0x40); in platinumfb_probe()
/drivers/block/
Dswim3.c276 out_8(&sw->select, RELAX); in swim3_select()
278 out_8(&sw->control_bis, SELECT); in swim3_select()
280 out_8(&sw->control_bic, SELECT); in swim3_select()
281 out_8(&sw->select, sel & CA_MASK); in swim3_select()
290 out_8(&sw->select, sw->select | LSTRB); in swim3_action()
292 out_8(&sw->select, sw->select & ~LSTRB); in swim3_action()
379 out_8(&sw->intr_enable, SEEN_SECTOR); in scan_track()
380 out_8(&sw->control_bis, DO_ACTION); in scan_track()
400 out_8(&sw->intr_enable, SEEK_DONE); in seek_track()
401 out_8(&sw->control_bis, DO_SEEK); in seek_track()
[all …]
/drivers/net/can/mscan/
Dmscan.c61 out_8(&regs->cantarq, priv->tx_active); in mscan_set_mode()
63 out_8(&regs->cantier, 0); in mscan_set_mode()
133 out_8(&regs->canrier, 0); in mscan_start()
145 out_8(&regs->canmisc, MSCAN_BOHOLD); in mscan_start()
156 out_8(&regs->cantier, 0); in mscan_start()
159 out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE); in mscan_start()
174 out_8(&regs->canmisc, MSCAN_BOHOLD); in mscan_restart()
176 out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE); in mscan_restart()
197 out_8(&regs->cantier, 0); in mscan_start_xmit()
225 out_8(&regs->cantbsel, i); in mscan_start_xmit()
[all …]
/drivers/net/ethernet/apple/
Dmace.c326 out_8(&mb->biucc, SWRST); in mace_reset()
338 out_8(&mb->imr, 0xff); /* disable all intrs for now */ in mace_reset()
340 out_8(&mb->maccc, 0); /* turn off tx, rx */ in mace_reset()
342 out_8(&mb->biucc, XMTSP_64); in mace_reset()
343 out_8(&mb->utr, RTRD); in mace_reset()
344 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST); in mace_reset()
345 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */ in mace_reset()
346 out_8(&mb->rcvfc, 0); in mace_reset()
353 out_8(&mb->iac, LOGADDR); in mace_reset()
355 out_8(&mb->iac, ADDRCHG | LOGADDR); in mace_reset()
[all …]
/drivers/spi/
Dspi-mpc52xx-psc.c145 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); in mpc52xx_psc_spi_transfer_rxtx()
160 out_8(&psc->ircr2, 0x01); in mpc52xx_psc_spi_transfer_rxtx()
163 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]); in mpc52xx_psc_spi_transfer_rxtx()
165 out_8(&psc->mpc52xx_psc_buffer_8, 0); in mpc52xx_psc_spi_transfer_rxtx()
173 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); in mpc52xx_psc_spi_transfer_rxtx()
175 out_8(&psc->mode, 0); in mpc52xx_psc_spi_transfer_rxtx()
177 out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); in mpc52xx_psc_spi_transfer_rxtx()
195 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); in mpc52xx_psc_spi_transfer_rxtx()
321 out_8(&psc->command, MPC52xx_PSC_RST_RX); in mpc52xx_psc_spi_port_config()
322 out_8(&psc->command, MPC52xx_PSC_RST_TX); in mpc52xx_psc_spi_port_config()
[all …]
Dspi-mpc52xx.c103 out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08); in mpc52xx_spi_chipsel()
125 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); in mpc52xx_spi_start_transfer()
127 out_8(ms->regs + SPI_DATA, 0); in mpc52xx_spi_start_transfer()
170 out_8(ms->regs + SPI_CTRL1, ctrl1); in mpc52xx_spi_fsmstate_idle()
189 out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */ in mpc52xx_spi_fsmstate_idle()
229 out_8(ms->regs + SPI_DATA, data); /* try again */ in mpc52xx_spi_fsmstate_transfer()
261 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); in mpc52xx_spi_fsmstate_transfer()
263 out_8(ms->regs + SPI_DATA, 0); in mpc52xx_spi_fsmstate_transfer()
398 out_8(regs + SPI_CTRL1, ctrl1); in mpc52xx_spi_probe()
399 out_8(regs + SPI_CTRL2, 0x0); in mpc52xx_spi_probe()
[all …]
Dspi-mpc512x-psc.c186 out_8(&fifo->txdata_8, data); in mpc512x_psc_spi_transfer_rxtx()
341 out_8(psc_addr(mps, mr2), 0x0); in mpc512x_psc_spi_prep_xfer_hw()
344 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); in mpc512x_psc_spi_prep_xfer_hw()
357 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); in mpc512x_psc_spi_unprep_xfer_hw()
414 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX); in mpc512x_psc_spi_port_config()
415 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX); in mpc512x_psc_spi_port_config()
416 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); in mpc512x_psc_spi_port_config()
445 out_8(psc_addr(mps, ctur), 0x00); in mpc512x_psc_spi_port_config()
446 out_8(psc_addr(mps, ctlr), 0x82); in mpc512x_psc_spi_port_config()
Dspi-ppc4xx.c155 out_8(&hw->regs->txd, data); in spi_ppc4xx_txrx()
156 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); in spi_ppc4xx_txrx()
188 out_8(&hw->regs->mode, cs->mode); in spi_ppc4xx_setupxfer()
199 out_8(&hw->regs->cdm, cdm); in spi_ppc4xx_setupxfer()
306 out_8(&hw->regs->txd, data); in spi_ppc4xx_int()
307 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); in spi_ppc4xx_int()
/drivers/tty/serial/cpm_uart/
Dcpm_uart_cpm1.h21 out_8(&sup->scc_genscc.scc_rfcr, SMC_EB); in cpm_set_scc_fcr()
22 out_8(&sup->scc_genscc.scc_tfcr, SMC_EB); in cpm_set_scc_fcr()
27 out_8(&up->smc_rfcr, SMC_EB); in cpm_set_smc_fcr()
28 out_8(&up->smc_tfcr, SMC_EB); in cpm_set_smc_fcr()
Dcpm_uart_cpm2.h21 out_8(&sup->scc_genscc.scc_rfcr, CPMFCR_GBL | CPMFCR_EB); in cpm_set_scc_fcr()
22 out_8(&sup->scc_genscc.scc_tfcr, CPMFCR_GBL | CPMFCR_EB); in cpm_set_scc_fcr()
27 out_8(&up->smc_rfcr, CPMFCR_GBL | CPMFCR_EB); in cpm_set_smc_fcr()
28 out_8(&up->smc_tfcr, CPMFCR_GBL | CPMFCR_EB); in cpm_set_smc_fcr()
/drivers/tty/serial/
Dmpc52xx_uart.c127 out_8(&psc->ctur, divisor >> 8); in mpc52xx_set_divisor()
128 out_8(&psc->ctlr, divisor & 0xff); in mpc52xx_set_divisor()
143 out_8(&PSC(port)->command, cmd); in mpc52xx_psc_command()
148 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); in mpc52xx_psc_set_mode()
149 out_8(&PSC(port)->mode, mr1); in mpc52xx_psc_set_mode()
150 out_8(&PSC(port)->mode, mr2); in mpc52xx_psc_set_mode()
156 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); in mpc52xx_psc_set_rts()
158 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); in mpc52xx_psc_set_rts()
168 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); in mpc52xx_psc_enable_ms()
186 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); in mpc52xx_psc_get_mr1()
[all …]
/drivers/gpio/
Dgpio-mpc5200.c69 out_8(&regs->wkup_dvo, chip->shadow_dvo); in __mpc52xx_wkup_gpio_set()
97 out_8(&regs->wkup_ddr, chip->shadow_ddr); in mpc52xx_wkup_gpio_dir_in()
101 out_8(&regs->wkup_gpioe, chip->shadow_gpioe); in mpc52xx_wkup_gpio_dir_in()
122 out_8(&regs->wkup_ddr, chip->shadow_ddr); in mpc52xx_wkup_gpio_dir_out()
126 out_8(&regs->wkup_gpioe, chip->shadow_gpioe); in mpc52xx_wkup_gpio_dir_out()
/drivers/tty/serial/8250/
D8250_hp300.c140 out_8(pa + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE); in hp300_setup_serial_console()
190 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE); in hpdca_init_one()
194 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff); in hpdca_init_one()
295 out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, 0); in hpdca_remove_one()
/drivers/net/ethernet/amd/
Dhplance.c135 out_8(va + DIO_IDOFF, 0xff); in hplance_init()
208 out_8(lp->base + HPLANCE_STATUS, LE_IE); in hplance_open()
217 out_8(lp->base + HPLANCE_STATUS, 0); /* disable interrupts at boardlevel */ in hplance_close()

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