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Searched refs:output_rate (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/mstar/
Dclk-msc313-mpll.c49 unsigned long output_rate; in msc313_mpll_recalc_rate() local
56 output_rate = parent_rate / (1 << input_div); in msc313_mpll_recalc_rate()
57 output_rate *= (1 << loop_first) * max(loop_second, 1U); in msc313_mpll_recalc_rate()
58 output_rate /= max(output_div, 1U); in msc313_mpll_recalc_rate()
60 return output_rate; in msc313_mpll_recalc_rate()
/drivers/clk/tegra/
Dclk-divider.c66 unsigned long output_rate = *prate; in clk_frac_div_round_rate() local
69 return output_rate; in clk_frac_div_round_rate()
71 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
77 return DIV_ROUND_UP(output_rate * mul, div + mul); in clk_frac_div_round_rate()
Dclk-sdmmc-mux.c112 unsigned long output_rate = req->best_parent_rate; in clk_sdmmc_mux_determine_rate() local
118 return output_rate; in clk_sdmmc_mux_determine_rate()
120 div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags); in clk_sdmmc_mux_determine_rate()
125 req->rate = DIV_ROUND_UP(output_rate * SDMMC_MUL, in clk_sdmmc_mux_determine_rate()
128 req->rate = output_rate * SDMMC_MUL / (div + SDMMC_MUL); in clk_sdmmc_mux_determine_rate()
Dclk-pll.c528 sel->output_rate == rate) in _get_table_rate()
543 cfg->output_rate = sel->output_rate; in _get_table_rate()
590 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; in _calc_rate()
591 cfg->output_rate <<= 1) in _calc_rate()
595 cfg->n = cfg->output_rate / cfreq; in _calc_rate()
600 cfg->output_rate > pll->params->vco_max) { in _calc_rate()
604 cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m); in _calc_rate()
605 cfg->output_rate >>= p_div; in _calc_rate()
860 return cfg.output_rate; in clk_pll_round_rate()
1233 cfg->output_rate = rate * p; in _calc_dynamic_ramp_rate()
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Dclk-tegra210.c1514 cfg->output_rate = input_rate; in tegra210_pll_fixed_mdiv_cfg()
1525 cfg->output_rate *= sdin_get_n_eff(cfg); in tegra210_pll_fixed_mdiv_cfg()
1526 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF; in tegra210_pll_fixed_mdiv_cfg()
1528 cfg->output_rate *= cfg->n; in tegra210_pll_fixed_mdiv_cfg()
1529 cfg->output_rate /= p * cfg->m; in tegra210_pll_fixed_mdiv_cfg()
Dclk.h166 unsigned long output_rate; member