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Searched refs:pfctx (Results 1 – 5 of 5) sorted by relevance

/drivers/net/ethernet/mellanox/mlx4/
Den_main.c70 MLX4_EN_PARM_INT(pfctx, 0, "Priority based Flow Control policy on TX[7:0]."
166 params->prof[i].rx_pause = !(pfcrx || pfctx); in mlx4_en_get_profile()
168 params->prof[i].tx_pause = !(pfcrx || pfctx); in mlx4_en_get_profile()
169 params->prof[i].tx_ppp = pfctx; in mlx4_en_get_profile()
365 if (pfctx > MAX_PFC_TX) { in mlx4_en_verify_params()
367 pfctx, MAX_PFC_TX); in mlx4_en_verify_params()
368 pfctx = 0; in mlx4_en_verify_params()
Dport.c1609 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx) in mlx4_SET_PORT_general() argument
1622 context->pptx = (pptx * (!pfctx)) << 7; in mlx4_SET_PORT_general()
1623 context->pfctx = pfctx; in mlx4_SET_PORT_general()
Dmlx4.h801 u8 pfctx; member
/drivers/net/ethernet/mellanox/mlx5/core/
Dport.c595 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx); in mlx5_set_port_pfc()
615 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx); in mlx5_query_port_pfc()
/drivers/net/ethernet/mellanox/mlxsw/
Dreg.h4865 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);