Searched refs:phyclk_khz (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 228 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
233 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rv1_update_clocks()
234 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in rv1_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 344 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { in dcn2_update_clocks_fpga()
345 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn2_update_clocks_fpga()
503 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { in dcn2_notify_link_rate_change()
504 clk_mgr_base->clks.phyclk_khz = max_phyclk_req; in dcn2_notify_link_rate_change()
505 …voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz)); in dcn2_notify_link_rate_change()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| D | dce120_clk_mgr.c | 112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_trace.h | 499 __field(int, phyclk_khz)
517 __entry->phyclk_khz = clk->phyclk_khz;
542 __entry->phyclk_khz,
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 497 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { in dcn30_notify_link_rate_change()
498 clk_mgr_base->clks.phyclk_khz = max_phyclk_req; in dcn30_notify_link_rate_change()
499 …30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz)); in dcn30_notify_link_rate_change()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 561 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { in rn_notify_link_rate_change()
562 clk_mgr_base->clks.phyclk_khz = max_phyclk_req; in rn_notify_link_rate_change()
563 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz); in rn_notify_link_rate_change()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clk_mgr.c | 779 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) { in dce12_update_clocks()
782 clk_mgr->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 385 int phyclk_khz; member
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 1193 context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level]; in dcn_validate_bandwidth()
1437 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz); in dcn_find_dcfclk_suits_all()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 2936 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_prepare_bandwidth()
2969 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_optimize_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 3617 info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz; in get_clock_requirements_for_state()
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