| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 133 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
203 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
248 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
302 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
341 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
394 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_mpcc_states()
509 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
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| D | dcn10_hw_sequencer.c | 101 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
171 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
203 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
228 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
260 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
293 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
335 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
720 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
764 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_bios_golden_init()
791 for (i = 0; i < dc->res_pool->pipe_count; i++) { in false_optc_underflow_wa()
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| D | dcn10_resource.c | 986 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1410 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1413 pool->base.pipe_count = 3; in dcn10_resource_construct()
1569 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1638 pool->base.pipe_count = j; in dcn10_resource_construct()
1644 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1645 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1667 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 805 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
878 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
964 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1045 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1107 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1165 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1245 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1307 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1365 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1441 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 800 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
873 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_validate_bandwidth()
959 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1034 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1096 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1154 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1232 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1294 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1352 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1426 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
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| D | dce60_hw_sequencer.c | 70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 816 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
979 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1267 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1268 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1269 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1270 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1271 pool->pipe_count++; in underlay_create()
1365 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1366 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1440 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
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| D | dce110_hw_sequencer.c | 1622 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vga_and_power_gate_all_controllers()
1943 for (i = 0; i < dc->res_pool->pipe_count; i++) { in should_enable_fbc()
1959 if (i == dc->res_pool->pipe_count) in should_enable_fbc()
2106 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2152 if (i == dc->res_pool->pipe_count) { in dce110_setup_audio_dto()
2153 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2203 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2228 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2531 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
2559 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 950 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
975 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1017 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
1116 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1210 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1213 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1236 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1239 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1246 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1260 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
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| D | dc_surface.c | 150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
162 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
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| D | dc_debug.c | 318 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
330 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1485 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1728 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1991 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
2015 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
2410 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
2456 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
2526 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
2549 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
2571 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
2600 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
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| D | dcn20_hwseq.c | 1466 int opp_count = dc->res_pool->pipe_count; in dcn20_update_dchubp_dpp()
1687 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1698 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1711 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1716 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1725 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1740 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1774 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
1784 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
1797 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1241 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1322 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1359 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1361 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1384 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1386 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1469 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1488 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_writeback_from_context()
1605 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1737 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 845 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() local
847 for (i = 0; i < pipe_count; i++) { in dcn302_dwbc_create()
880 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() local
882 for (i = 0; i < pipe_count; i++) { in dcn302_mmhubbub_create()
1105 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
1106 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1166 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1241 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1506 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1640 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 787 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() local
789 for (i = 0; i < pipe_count; i++) { in dcn303_dwbc_create()
822 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() local
824 for (i = 0; i < pipe_count; i++) { in dcn303_mmhubbub_create()
1031 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
1032 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1092 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1167 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1446 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1571 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1272 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_destruct()
1384 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create() local
1386 for (i = 0; i < pipe_count; i++) { in dcn301_dwbc_create()
1409 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create() local
1411 for (i = 0; i < pipe_count; i++) { in dcn301_mmhubbub_create()
1510 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1586 dcn3_01_ip.max_num_dpp = pool->base.pipe_count; in dcn301_update_bw_bounding_box()
1701 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn301_calculate_wm_and_dlg()
1766 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1907 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 943 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_destruct()
1113 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
1235 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1259 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1343 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn21_validate_bandwidth_fp()
1600 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; in update_bw_bounding_box()
1979 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
2035 pool->base.pipe_count = 4; in dcn21_resource_construct()
2146 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_construct()
2214 pool->base.pipe_count = j; in dcn21_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1368 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_destruct()
1483 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1485 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1508 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1510 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1593 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1772 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
1815 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn31_validate_bandwidth()
1875 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
2002 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
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| D | dcn31_hwseq.c | 277 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_init_hw()
575 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { in dcn31_reset_hw_ctx_wrap()
604 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_is_abm_supported()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 757 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
844 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
1065 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1076 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_construct()
1139 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 601 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_destruct()
1071 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1160 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_construct()
1236 pool->base.pipe_count = j; in dce120_resource_construct()
1251 dc->caps.max_planes = pool->base.pipe_count; in dce120_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn2x/ |
| D | dcn2x.c | 72 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
143 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
174 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 778 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_destruct()
901 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
1234 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1321 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_construct()
1390 dc->caps.max_planes = pool->base.pipe_count; in dce112_resource_construct()
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