| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_hw_sequencer.c | 55 struct pipe_ctx *pipe_ctx = NULL; in dce60_should_enable_fbc() local
71 if (res_ctx->pipe_ctx[i].stream) { in dce60_should_enable_fbc()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dce60_should_enable_fbc()
75 if (!pipe_ctx) in dce60_should_enable_fbc()
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
89 if (!pipe_ctx->stream->link) in dce60_should_enable_fbc()
93 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) in dce60_should_enable_fbc()
97 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) in dce60_should_enable_fbc()
101 if (!pipe_ctx->plane_state) in dce60_should_enable_fbc()
105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.h | 36 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
39 struct pipe_ctx *pipe_ctx,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
44 struct pipe_ctx *pipe_ctx,
55 struct pipe_ctx *pipe,
57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
60 struct pipe_ctx *pipe_ctx,
62 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
65 struct pipe_ctx *pipe_ctx,
69 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
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| D | dcn10_hw_sequencer.c | 97 struct pipe_ctx *pipe_ctx; in dcn10_lock_all_pipes() local
102 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
103 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
109 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
110 !pipe_ctx->stream || !pipe_ctx->plane_state || in dcn10_lock_all_pipes()
115 dc->hwss.pipe_control_lock(dc, pipe_ctx, true); in dcn10_lock_all_pipes()
117 dc->hwss.pipe_control_lock(dc, pipe_ctx, false); in dcn10_lock_all_pipes()
472 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn10_did_underflow_occur() argument
474 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur()
475 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_did_underflow_occur()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer.h | 35 struct pipe_ctx;
61 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
72 struct pipe_ctx *pipe_ctx);
77 struct pipe_ctx *pipe_ctx);
82 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);
83 void (*update_pending_status)(struct pipe_ctx *pipe_ctx);
88 struct pipe_ctx *pipe, bool lock);
91 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,
93 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);
96 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
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| D | hw_sequencer_private.h | 52 struct pipe_ctx;
72 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
73 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
77 struct pipe_ctx *pipe_ctx);
79 struct pipe_ctx *pipe_ctx);
80 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
82 struct pipe_ctx *pipe_ctx,
85 struct pipe_ctx *pipe_ctx,
95 struct pipe_ctx *pipe_ctx,
98 struct pipe_ctx *pipe_ctx,
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| D | resource.h | 92 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
98 void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
125 struct pipe_ctx *pipe_ctx);
131 struct pipe_ctx *resource_get_head_pipe_for_stream(
142 struct pipe_ctx *find_idle_secondary_pipe(
145 const struct pipe_ctx *primary_pipe);
169 struct pipe_ctx *pipe_ctx_old,
170 struct pipe_ctx *pipe_ctx);
186 int get_num_mpc_splits(struct pipe_ctx *pipe);
188 int get_num_odm_splits(struct pipe_ctx *pipe);
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| D | dc_link_dp.h | 85 struct pipe_ctx *pipe_ctx,
167 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
168 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
169 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
170 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
171 bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 96 struct pipe_ctx *pipe_ctx, in dcn20_setup_gsl_group_as_lock() argument
108 if (pipe_ctx->stream_res.gsl_group > 0) in dcn20_setup_gsl_group_as_lock()
113 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
135 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
139 pipe_ctx->stream_res.gsl_group = 0; in dcn20_setup_gsl_group_as_lock()
163 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && in dcn20_setup_gsl_group_as_lock()
164 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { in dcn20_setup_gsl_group_as_lock()
165 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
166 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
169 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
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| D | dcn20_hwseq.h | 32 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
41 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
42 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
43 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
45 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
48 struct pipe_ctx *pipe_ctx,
52 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
53 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
55 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 282 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_input_transfer_func() argument
285 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
610 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_output_transfer_func() argument
613 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
635 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) in dce110_update_info_frame() argument
640 ASSERT(pipe_ctx->stream); in dce110_update_info_frame()
642 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
645 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
646 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
652 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
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| D | dce110_hw_sequencer.h | 43 void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
45 void dce110_disable_stream(struct pipe_ctx *pipe_ctx);
47 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
50 void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
52 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
53 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
55 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
57 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
88 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
91 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_resource.c | 537 const struct pipe_ctx *pipe_with_clk_src, in is_sharable_clk_src()
538 const struct pipe_ctx *pipe) in is_sharable_clk_src()
569 struct pipe_ctx *pipe_ctx) in resource_find_used_clk_src_for_sharing() argument
574 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) in resource_find_used_clk_src_for_sharing()
575 return res_ctx->pipe_ctx[i].clock_source; in resource_find_used_clk_src_for_sharing()
657 int get_num_mpc_splits(struct pipe_ctx *pipe) in get_num_mpc_splits()
660 struct pipe_ctx *other_pipe = pipe->bottom_pipe; in get_num_mpc_splits()
675 int get_num_odm_splits(struct pipe_ctx *pipe) in get_num_odm_splits()
678 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; in get_num_odm_splits()
691 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split… in calculate_split_count_and_index() argument
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| D | dc_link.c | 1684 static void enable_stream_features(struct pipe_ctx *pipe_ctx) in enable_stream_features() argument
1686 struct dc_stream_state *stream = pipe_ctx->stream; in enable_stream_features()
1688 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { in enable_stream_features()
1714 struct pipe_ctx *pipe_ctx) in enable_link_dp() argument
1716 struct dc_stream_state *stream = pipe_ctx->stream; in enable_link_dp()
1740 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { in enable_link_dp()
1746 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = in enable_link_dp()
1765 pipe_ctx, in enable_link_dp()
1766 pipe_ctx->stream->signal, in enable_link_dp()
1796 struct pipe_ctx *pipe_ctx) in enable_link_edp() argument
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| D | dc_link_hwss.c | 74 struct pipe_ctx *pipes = in dp_enable_link_phy()
75 link->dc->current_state->res_ctx.pipe_ctx; in dp_enable_link_phy()
329 struct pipe_ctx *pipes = in dp_retrain_link_dp_test()
330 &link->dc->current_state->res_ctx.pipe_ctx[0]; in dp_retrain_link_dp_test()
415 bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) in dp_set_dsc_on_rx() argument
417 struct dc *dc = pipe_ctx->stream->ctx->dc; in dp_set_dsc_on_rx()
418 struct dc_stream_state *stream = pipe_ctx->stream; in dp_set_dsc_on_rx()
431 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) in dp_set_dsc_on_stream() argument
433 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in dp_set_dsc_on_stream()
434 struct dc *dc = pipe_ctx->stream->ctx->dc; in dp_set_dsc_on_stream()
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| D | dc_stream.c | 256 struct pipe_ctx *pipe_to_program = NULL; in program_cursor_attributes()
264 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_attributes() local
266 if (pipe_ctx->stream != stream) in program_cursor_attributes()
270 pipe_to_program = pipe_ctx; in program_cursor_attributes()
274 dc->hwss.set_cursor_attribute(pipe_ctx); in program_cursor_attributes()
276 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in program_cursor_attributes()
356 struct pipe_ctx *pipe_to_program = NULL; in program_cursor_position()
364 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_position() local
366 if (pipe_ctx->stream != stream || in program_cursor_position()
367 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
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| D | dc.c | 315 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax()
351 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_last_used_drr_vtotal()
381 struct pipe_ctx *pipe = in dc_stream_get_crtc_position()
382 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crtc_position()
401 struct pipe_ctx *pipe; in dc_stream_forward_dmcu_crc_window()
419 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_dmcu_crc_window()
446 struct pipe_ctx *pipe; in dc_stream_stop_dmcu_crc_win_update()
453 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_stop_dmcu_crc_win_update()
493 struct pipe_ctx *pipe; in dc_stream_configure_crc()
498 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_configure_crc()
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| D | dc_hw_sequencer.c | 296 struct pipe_ctx *pipe_ctx, in get_mpctree_visual_confirm_color() argument
308 struct pipe_ctx *top_pipe = pipe_ctx; in get_mpctree_visual_confirm_color()
317 const struct pipe_ctx *pipe_ctx, in get_surface_visual_confirm_color() argument
322 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
326 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
336 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
355 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
367 struct pipe_ctx *pipe_ctx, in get_hdr_visual_confirm_color() argument
373 struct pipe_ctx *top_pipe_ctx = pipe_ctx; in get_hdr_visual_confirm_color()
408 struct pipe_ctx *pipe_ctx, in get_surface_tile_visual_confirm_color() argument
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| /drivers/gpu/drm/amd/display/dc/basics/ |
| D | dc_common.c | 52 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) in is_lower_pipe_tree_visible() argument
54 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_lower_pipe_tree_visible()
56 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) in is_lower_pipe_tree_visible()
61 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) in is_upper_pipe_tree_visible() argument
63 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_upper_pipe_tree_visible()
65 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_upper_pipe_tree_visible()
70 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) in is_pipe_tree_visible() argument
72 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_pipe_tree_visible()
74 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_pipe_tree_visible()
76 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) in is_pipe_tree_visible()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hwseq.c | 129 void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx) in dcn21_PLAT_58856_wa() argument
131 if (!pipe_ctx->stream->dpms_off) in dcn21_PLAT_58856_wa()
134 pipe_ctx->stream->dpms_off = false; in dcn21_PLAT_58856_wa()
135 core_link_enable_stream(context, pipe_ctx); in dcn21_PLAT_58856_wa()
136 core_link_disable_stream(pipe_ctx); in dcn21_PLAT_58856_wa()
137 pipe_ctx->stream->dpms_off = true; in dcn21_PLAT_58856_wa()
162 void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) in dcn21_set_abm_immediate_disable() argument
164 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
165 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
166 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; in dcn21_set_abm_immediate_disable()
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| D | dcn21_hwseq.h | 48 struct pipe_ctx *pipe_ctx);
50 void dcn21_set_pipe(struct pipe_ctx *pipe_ctx);
51 void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);
52 bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 384 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) in dcn31_update_info_frame() argument
389 ASSERT(pipe_ctx->stream); in dcn31_update_info_frame()
391 if (pipe_ctx->stream_res.stream_enc == NULL) in dcn31_update_info_frame()
394 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dcn31_update_info_frame()
395 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dcn31_update_info_frame()
401 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dcn31_update_info_frame()
402 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
403 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
405 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( in dcn31_update_info_frame()
406 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.h | 55 bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
59 struct pipe_ctx *pipe_ctx,
62 struct pipe_ctx *pipe_ctx,
64 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
65 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
66 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
76 struct pipe_ctx *pipe_ctx,
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| D | dcn30_hwseq.c | 72 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) in dcn30_set_blend_lut() argument
74 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
93 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) in dcn30_set_mpc_shaper_3dlut() argument
95 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
96 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut()
97 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
145 struct pipe_ctx *pipe_ctx, in dcn30_set_input_transfer_func() argument
149 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
176 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { in dcn30_set_input_transfer_func()
178 hws->funcs.set_blend_lut(pipe_ctx, plane_state); in dcn30_set_input_transfer_func()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_trace.h | 26 #define TRACE_DC_PIPE_STATE(pipe_ctx, index, max_pipes) \ argument
28 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \
29 if (pipe_ctx->plane_state) \
30 trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \
31 pipe_ctx->stream, &pipe_ctx->plane_res, \
32 pipe_ctx->update_flags.raw); \
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_debugfs.c | 1305 struct pipe_ctx *pipe_ctx; in dp_dsc_clock_en_read() local
1317 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_clock_en_read()
1318 if (pipe_ctx && pipe_ctx->stream && in dp_dsc_clock_en_read()
1319 pipe_ctx->stream->link == aconnector->dc_link) in dp_dsc_clock_en_read()
1323 if (!pipe_ctx) { in dp_dsc_clock_en_read()
1328 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_clock_en_read()
1390 struct pipe_ctx *pipe_ctx; in dp_dsc_clock_en_write() local
1423 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_clock_en_write()
1424 if (pipe_ctx && pipe_ctx->stream && in dp_dsc_clock_en_write()
1425 pipe_ctx->stream->link == aconnector->dc_link) in dp_dsc_clock_en_write()
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