| /drivers/gpu/drm/amd/display/dc/dml/dcn2x/ |
| D | dcn2x.c | 66 display_e2e_pipe_params_st *pipes) in dcn20_populate_dml_writeback_from_context() argument
79 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
80 pipes[pipe_cnt].dout.num_active_wb++; in dcn20_populate_dml_writeback_from_context()
81 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
82 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
83 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
84 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
85 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
86 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
87 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; in dcn20_populate_dml_writeback_from_context()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1984 display_e2e_pipe_params_st *pipes, in dcn20_populate_dml_pipes_from_context() argument
2033 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_populate_dml_pipes_from_context()
2035 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; in dcn20_populate_dml_pipes_from_context()
2037 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; in dcn20_populate_dml_pipes_from_context()
2039 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true; in dcn20_populate_dml_pipes_from_context()
2041 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = in dcn20_populate_dml_pipes_from_context()
2045 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = in dcn20_populate_dml_pipes_from_context()
2048 pipes[pipe_cnt].pipe.src.dcc = false; in dcn20_populate_dml_pipes_from_context()
2049 pipes[pipe_cnt].pipe.src.dcc_rate = 1; in dcn20_populate_dml_pipes_from_context()
2050 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; in dcn20_populate_dml_pipes_from_context()
[all …]
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| D | dcn20_resource.h | 55 display_e2e_pipe_params_st *pipes,
119 display_e2e_pipe_params_st *pipes,
156 display_e2e_pipe_params_st *pipes,
163 display_e2e_pipe_params_st *pipes,
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_hwss.c | 74 struct pipe_ctx *pipes = in dp_enable_link_phy() local
97 if (pipes[i].stream != NULL && in dp_enable_link_phy()
98 pipes[i].stream->link == link) { in dp_enable_link_phy()
99 if (pipes[i].clock_source != NULL && in dp_enable_link_phy()
100 pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { in dp_enable_link_phy()
101 pipes[i].clock_source = dp_cs; in dp_enable_link_phy()
102 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz = in dp_enable_link_phy()
103 pipes[i].stream->timing.pix_clk_100hz; in dp_enable_link_phy()
104 pipes[i].clock_source->funcs->program_pix_clk( in dp_enable_link_phy()
105 pipes[i].clock_source, in dp_enable_link_phy()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1584 display_e2e_pipe_params_st *pipes, in dcn31_populate_dml_pipes_from_context() argument
1591 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); in dcn31_populate_dml_pipes_from_context()
1606 pipes[pipe_cnt].pipe.src.immediate_flip = true; in dcn31_populate_dml_pipes_from_context()
1608 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; in dcn31_populate_dml_pipes_from_context()
1609 pipes[pipe_cnt].pipe.src.gpuvm = true; in dcn31_populate_dml_pipes_from_context()
1610 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn31_populate_dml_pipes_from_context()
1611 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn31_populate_dml_pipes_from_context()
1612 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; in dcn31_populate_dml_pipes_from_context()
1613 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn31_populate_dml_pipes_from_context()
1614 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn31_populate_dml_pipes_from_context()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_vba.c | 46 const display_e2e_pipe_params_st *pipes,
53 const display_e2e_pipe_params_st *pipes, in dml_get_voltage_level() argument
59 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
64 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
67 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
80 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
82 recalculate_params(mode_lib, pipes, num_pipes); \
112 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
115 recalculate_params(mode_lib, pipes, num_pipes); \
169 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bytes() argument
[all …]
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| D | display_mode_lib.c | 137 display_e2e_pipe_params_st *pipes, in dml_log_pipe_params() argument
149 pipe_src = &(pipes[i].pipe.src); in dml_log_pipe_params()
150 pipe_dest = &(pipes[i].pipe.dest); in dml_log_pipe_params()
151 scale_ratio_depth = &(pipes[i].pipe.scale_ratio_depth); in dml_log_pipe_params()
152 scale_taps = &(pipes[i].pipe.scale_taps); in dml_log_pipe_params()
153 dout = &(pipes[i].dout); in dml_log_pipe_params()
154 clks_cfg = &(pipes[i].clks_cfg); in dml_log_pipe_params()
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| /drivers/platform/goldfish/ |
| D | goldfish_pipe.c | 198 struct goldfish_pipe **pipes; member
522 pipe = dev->pipes[id]; in signalled_pipes_add_locked()
654 if (!dev->pipes[id]) in get_free_pipe_id_locked()
663 struct goldfish_pipe **pipes = in get_free_pipe_id_locked() local
664 kcalloc(new_capacity, sizeof(*pipes), GFP_ATOMIC); in get_free_pipe_id_locked()
665 if (!pipes) in get_free_pipe_id_locked()
667 memcpy(pipes, dev->pipes, sizeof(*pipes) * dev->pipes_capacity); in get_free_pipe_id_locked()
668 kfree(dev->pipes); in get_free_pipe_id_locked()
669 dev->pipes = pipes; in get_free_pipe_id_locked()
732 dev->pipes[id] = pipe; in goldfish_pipe_open()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1461 display_e2e_pipe_params_st *pipes, in dcn30_populate_dml_pipes_from_context() argument
1467 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); in dcn30_populate_dml_pipes_from_context()
1473 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth = in dcn30_populate_dml_pipes_from_context()
1481 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_populate_dml_writeback_from_context() argument
1496 pipes[pipe_cnt].dout.wb_enable = 0; in dcn30_populate_dml_writeback_from_context()
1497 pipes[pipe_cnt].dout.num_active_wb = 0; in dcn30_populate_dml_writeback_from_context()
1503 pipes[pipe_cnt].dout.wb_enable = 1; in dcn30_populate_dml_writeback_from_context()
1504 pipes[pipe_cnt].dout.num_active_wb++; in dcn30_populate_dml_writeback_from_context()
1547 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, in dcn30_populate_dml_writeback_from_context()
1554 pipes[pipe_cnt].pipe.dest.htotal, in dcn30_populate_dml_writeback_from_context()
[all …]
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| D | dcn30_resource.h | 48 display_e2e_pipe_params_st *pipes,
61 display_e2e_pipe_params_st *pipes,
67 display_e2e_pipe_params_st *pipes,
72 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
76 display_e2e_pipe_params_st *pipes,
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 711 display_e2e_pipe_params_st *pipes,
1039 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel() argument
1046 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
1047 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1048 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
1054 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
1055 …wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) … in calculate_wm_set_for_vlevel()
1056 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
1057 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
1058 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
[all …]
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| /drivers/gpu/drm/arm/display/komeda/ |
| D | komeda_event.c | 110 return (a->pipes[0] | a->pipes[1]) & in is_new_frame()
120 u64 evts_mask = evts->global | evts->pipes[0] | evts->pipes[1]; in komeda_print_events()
147 evt_str(&str, evts->pipes[0]); in komeda_print_events()
149 evt_str(&str, evts->pipes[1]); in komeda_print_events()
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| /drivers/gpu/drm/tidss/ |
| D | tidss_kms.c | 123 struct pipe pipes[TIDSS_MAX_PORTS]; in tidss_dispc_modeset_init() local
181 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
182 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
183 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
209 tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, in tidss_dispc_modeset_init()
218 enc = tidss_encoder_create(tidss, pipes[i].enc_type, in tidss_dispc_modeset_init()
225 ret = drm_bridge_attach(enc, pipes[i].bridge, NULL, 0); in tidss_dispc_modeset_init()
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_drv.c | 136 struct omap_drm_pipeline *pipe = &priv->pipes[i]; in omap_disconnect_pipelines()
166 pipe = &priv->pipes[priv->num_pipes++]; in omap_connect_pipelines()
169 if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) { in omap_connect_pipelines()
281 struct omap_drm_pipeline *pipe = &priv->pipes[i]; in omap_modeset_init()
301 sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]), in omap_modeset_init()
309 struct omap_drm_pipeline *pipe = &priv->pipes[i]; in omap_modeset_init()
320 struct omap_drm_pipeline *pipe = &priv->pipes[i]; in omap_modeset_init()
386 struct drm_connector *connector = priv->pipes[i].connector; in omap_modeset_enable_external_hpd()
391 if (priv->pipes[i].output->bridge) in omap_modeset_enable_external_hpd()
405 struct drm_connector *connector = priv->pipes[i].connector; in omap_modeset_disable_external_hpd()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1634 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel() argument
1641 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
1642 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1643 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
1649 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
1650 …wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) … in calculate_wm_set_for_vlevel()
1651 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
1652 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
1653 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
1654 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
[all …]
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| /drivers/gpu/drm/arm/display/komeda/d71/ |
| D | d71_dev.c | 188 evts->pipes[0] |= KOMEDA_EVENT_FLIP; in d71_irq_handler()
190 evts->pipes[1] |= KOMEDA_EVENT_FLIP; in d71_irq_handler()
204 evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status); in d71_irq_handler()
207 evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status); in d71_irq_handler()
227 pipe = d71->pipes[i]; in d71_enable_irq()
246 pipe = d71->pipes[i]; in d71_disable_irq()
260 struct d71_pipeline *pipe = d71->pipes[master_pipe]; in d71_on_off_vblank()
435 d71->pipes[i] = to_d71_pipeline(pipe); in d71_enum_resources()
578 malidp_write32_mask(d71->pipes[i]->lpu_addr, LPU_TBU_CONTROL, in d71_connect_iommu()
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| D | d71_component.c | 415 c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*layer), in d71_layer_init()
534 c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*wb_layer), in d71_wb_layer_init()
675 c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*compiz), in d71_compiz_init()
844 c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*scaler), in d71_scaler_init()
952 c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*splitter), in d71_splitter_init()
1022 c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*merger), in d71_merger_init()
1133 c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*improc), in d71_improc_init()
1260 c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*ctrlr), in d71_timing_ctrlr_init()
1291 pipe = d71->pipes[blk_id]; in d71_probe_block()
1304 pipe = d71->pipes[blk_id]; in d71_probe_block()
[all …]
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| /drivers/net/wireless/ath/ath6kl/ |
| D | usb.c | 70 struct ath6kl_usb_pipe pipes[ATH6KL_USB_PIPE_MAX]; member
254 ath6kl_usb_free_pipe_resources(&ar_usb->pipes[i]); in ath6kl_usb_cleanup_pipe_resources()
357 pipe = &ar_usb->pipes[pipe_num]; in ath6kl_usb_setup_pipe_resources()
473 if (ar_usb->pipes[i].ar_usb != NULL) in ath6kl_usb_flush_all()
474 usb_kill_anchored_urbs(&ar_usb->pipes[i].urb_submitted); in ath6kl_usb_flush_all()
495 ar_usb->pipes[ATH6KL_USB_PIPE_RX_DATA].urb_cnt_thresh = 1; in ath6kl_usb_start_recv_pipes()
497 ath6kl_usb_post_recv_transfers(&ar_usb->pipes[ATH6KL_USB_PIPE_RX_DATA], in ath6kl_usb_start_recv_pipes()
644 pipe = &ar_usb->pipes[i]; in ath6kl_usb_create()
700 device->pipes[i].urb_cnt_thresh = in hif_start()
701 device->pipes[i].urb_alloc / 2; in hif_start()
[all …]
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| /drivers/net/wireless/ath/ath10k/ |
| D | usb.c | 120 ath10k_usb_free_pipe_resources(ar, &ar_usb->pipes[i]); in ath10k_usb_cleanup_pipe_resources()
264 if (ar_usb->pipes[i].ar_usb) { in ath10k_usb_flush_all()
265 usb_kill_anchored_urbs(&ar_usb->pipes[i].urb_submitted); in ath10k_usb_flush_all()
266 cancel_work_sync(&ar_usb->pipes[i].io_complete_work); in ath10k_usb_flush_all()
275 ar_usb->pipes[ATH10K_USB_PIPE_RX_DATA].urb_cnt_thresh = 1; in ath10k_usb_start_recv_pipes()
278 &ar_usb->pipes[ATH10K_USB_PIPE_RX_DATA]); in ath10k_usb_start_recv_pipes()
395 ar_usb->pipes[i].urb_cnt_thresh = in ath10k_usb_hif_start()
396 ar_usb->pipes[i].urb_alloc / 2; in ath10k_usb_hif_start()
406 struct ath10k_usb_pipe *pipe = &ar_usb->pipes[pipe_id]; in ath10k_usb_hif_tx_sg()
471 return ar_usb->pipes[pipe_id].urb_cnt; in ath10k_usb_hif_get_free_queue_number()
[all …]
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| /drivers/staging/media/atomisp/pci/ |
| D | sh_css.c | 132 struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM]; /* pipe handles */ member
401 struct ia_css_pipe *pipes[],
1477 assert(stream->pipes[i]); in sh_css_invalidate_shading_tables()
1478 sh_css_pipe_free_shading_table(stream->pipes[i]); in sh_css_invalidate_shading_tables()
1875 ia_css_pipeline_map(stream->pipes[i]->pipe_num, map); in map_sp_threads()
1970 main_pipe = stream->pipes[i]; in create_host_pipeline_structure()
2112 switch (stream->pipes[i]->mode) { in create_host_pipeline()
2114 err = create_host_preview_pipeline(stream->pipes[i]); in create_host_pipeline()
2117 err = create_host_video_pipeline(stream->pipes[i]); in create_host_pipeline()
2120 err = create_host_capture_pipeline(stream->pipes[i]); in create_host_pipeline()
[all …]
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| D | atomisp_compat_css20.c | 198 if (stream_env->pipes[pipe_id]) { in __dump_pipe_config()
296 if (stream_env->pipes[j]) { in __dump_stream_config()
493 if (stream_env->pipes[i]) in __create_stream()
494 multi_pipes[pipe_index++] = stream_env->pipes[i]; in __create_stream()
546 if (!stream_env->pipes[i] || in __destroy_stream_pipes()
549 if (ia_css_pipe_destroy(stream_env->pipes[i]) in __destroy_stream_pipes()
555 stream_env->pipes[i] = NULL; in __destroy_stream_pipes()
759 &stream_env->pipes[pipe_id]); in __create_pipe()
764 &stream_env->pipes[pipe_id]); in __create_pipe()
788 if (asd->stream_env[i].pipes[j]) { in __create_pipes()
[all …]
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 110 display_e2e_pipe_params_st *pipes,
118 display_e2e_pipe_params_st *pipes,
172 display_e2e_pipe_params_st *pipes);
177 display_e2e_pipe_params_st *pipes,
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| /drivers/nfc/st-nci/ |
| D | se.c | 230 ndev->hci_dev->pipes[pipe_info[2]].gate = in st_nci_hci_load_session()
232 ndev->hci_dev->pipes[pipe_info[2]].host = in st_nci_hci_load_session()
385 u8 gate = ndev->hci_dev->pipes[pipe].gate; in st_nci_hci_event_received()
386 u8 host = ndev->hci_dev->pipes[pipe].host; in st_nci_hci_event_received()
406 u8 gate = ndev->hci_dev->pipes[pipe].gate; in st_nci_hci_cmd_received()
413 ndev->hci_dev->pipes[pipe].host != ST_NCI_UICC_HOST_ID) in st_nci_hci_cmd_received()
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| /drivers/staging/media/ipu3/ |
| D | ipu3-css.c | 665 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_pipeline_cleanup()
699 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_pipeline_init()
1174 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_binary_cleanup()
1197 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_binary_preallocate()
1229 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_binary_setup()
1387 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_stop_streaming()
1408 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_pipe_queue_empty()
1437 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_map_init()
1481 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_pipe_cleanup()
1527 struct imgu_css_pipe *css_pipe = &css->pipes[pipe]; in imgu_css_init()
[all …]
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| /drivers/nfc/st21nfca/ |
| D | core.c | 185 hdev->pipes[pipe_info[2]].gate = in st21nfca_hci_load_session()
187 hdev->pipes[pipe_info[2]].dest_host = in st21nfca_hci_load_session()
836 u8 gate = hdev->pipes[pipe].gate; in st21nfca_hci_cmd_received()
843 hdev->pipes[pipe].dest_host != NFC_HCI_UICC_HOST_ID) in st21nfca_hci_cmd_received()
892 u8 gate = hdev->pipes[pipe].gate; in st21nfca_hci_event_received()
893 u8 host = hdev->pipes[pipe].dest_host; in st21nfca_hci_event_received()
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