Home
last modified time | relevance | path

Searched refs:plane_res (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c151 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in dce60_set_default_colors()
158 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in dce60_set_default_colors()
160 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( in dce60_set_default_colors()
161 pipe_ctx->plane_res.xfm, &default_adjust); in dce60_set_default_colors()
202 switch (pipe_ctx->plane_res.scl_data.format) { in dce60_get_surface_visual_confirm_color()
246 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in dce60_program_scaler()
247 pipe_ctx->plane_res.xfm, in dce60_program_scaler()
248 pipe_ctx->plane_res.scl_data.lb_params.depth, in dce60_program_scaler()
265 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
[all …]
/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c721 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_viewport_size()
738 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_recout()
823 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios()
826 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
831 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
833 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
835 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
836 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); in calculate_scaling_ratios()
837 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( in calculate_scaling_ratios()
838 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); in calculate_scaling_ratios()
[all …]
Ddc_stream.c367 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
369 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in program_cursor_position()
370 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in program_cursor_position()
685 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
Ddc_hw_sequencer.c322 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
378 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color()
Ddc.c627 if (pipes->plane_res.xfm && in dc_stream_set_dither_option()
628 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) { in dc_stream_set_dither_option()
629 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in dc_stream_set_dither_option()
630 pipes->plane_res.xfm, in dc_stream_set_dither_option()
631 pipes->plane_res.scl_data.lb_params.depth, in dc_stream_set_dither_option()
1753 mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; in dc_acquire_release_mpc_3dlut()
2966 cur_pipe.plane_res.hubp->funcs->validate_dml_output( in commit_planes_for_stream()
2967 cur_pipe.plane_res.hubp, dc->ctx, in commit_planes_for_stream()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c179 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) in dcn20_set_flip_control_gsl()
180 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( in dcn20_set_flip_control_gsl()
181 pipe_ctx->plane_res.hubp, flip_immediate); in dcn20_set_flip_control_gsl()
266 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
267 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_triple_buffer()
268 pipe_ctx->plane_res.hubp, in dcn20_program_triple_buffer()
570 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn20_plane_atomic_disable()
571 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable()
590 pipe_ctx->plane_res.dpp, in dcn20_plane_atomic_disable()
591 pipe_ctx->plane_res.hubp); in dcn20_plane_atomic_disable()
[all …]
Ddcn20_resource.c1878 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1879 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1880 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1881 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1882 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1883 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1901 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1918 sd = &next_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1963 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1964 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
[all …]
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c285 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
613 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
1346 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) in program_scaler()
1357 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in program_scaler()
1358 pipe_ctx->plane_res.xfm, in program_scaler()
1359 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1376 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler()
1377 &pipe_ctx->plane_res.scl_data); in program_scaler()
1531 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in apply_single_controller_ctx_to_hw()
1793 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_displaymarks()
[all …]
Ddce110_resource.c1136 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
1138 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; in dce110_acquire_underlay()
1172 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, in dce110_acquire_underlay()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
341 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
342 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
343 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
344 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
[all …]
Ddce_calcs.c2827 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2829 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data()
2830 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2831 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2832 …data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.h… in populate_initial_data()
2833 …data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.v… in populate_initial_data()
2882 …data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.v… in populate_initial_data()
2883 …data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.vi… in populate_initial_data()
2886 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2887 …data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c474 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur()
1009 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1034 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1047 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1057 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1069 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1107 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disconnect()
1108 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn10_plane_atomic_disconnect()
1123 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect()
1178 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disable()
[all …]
Ddcn10_resource.c1172 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1173 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1174 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1175 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_idle_pipe_for_layer()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c74 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
95 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
96 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut()
149 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
191 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func()
405 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
711 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn30_program_dmdata_engine()
996 pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true); in dcn30_set_disp_pattern_generator()
999 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); in dcn30_set_disp_pattern_generator()
1004 pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false); in dcn30_set_disp_pattern_generator()
[all …]
Ddcn30_resource.c1772 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1773 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1774 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1775 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1776 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1777 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
1941 && memcmp(&mpo_pipe->plane_res.scl_data.recout, in dcn30_internal_validate_bw()
1942 &pipe->plane_res.scl_data.recout, in dcn30_internal_validate_bw()
1973 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
1988 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_trace.h384 const struct plane_resource *plane_res,
386 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
437 __entry->recout_x = plane_res->scl_data.recout.x;
438 __entry->recout_y = plane_res->scl_data.recout.y;
439 __entry->recout_w = plane_res->scl_data.recout.width;
440 __entry->recout_h = plane_res->scl_data.recout.height;
441 __entry->viewport_x = plane_res->scl_data.viewport.x;
442 __entry->viewport_y = plane_res->scl_data.viewport.y;
443 __entry->viewport_w = plane_res->scl_data.viewport.width;
444 __entry->viewport_h = plane_res->scl_data.viewport.height;
/drivers/gpu/drm/amd/display/dc/dce/
Ddmub_psr.c280 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
282 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings()
283 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
/drivers/gpu/drm/amd/display/dc/
Ddc_trace.h31 pipe_ctx->stream, &pipe_ctx->plane_res, \
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c172 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
173 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h350 struct plane_resource plane_res; member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c116 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c115 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in rn_update_clocks_update_dpp_dto()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c1246 && memcmp(&mpo_pipe->plane_res.scl_data.recout, in dcn21_fast_validate_bw()
1247 &pipe->plane_res.scl_data.recout, in dcn21_fast_validate_bw()