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Searched refs:pll_req (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c554 struct fixed31_32 pll_req; in dcn20_clk_mgr_construct() local
561 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); in dcn20_clk_mgr_construct()
562 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; in dcn20_clk_mgr_construct()
565 pll_req = dc_fixpt_mul_int(pll_req, 100000); in dcn20_clk_mgr_construct()
568 clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req); in dcn20_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c226 struct fixed31_32 pll_req; in dcn30_get_vco_frequency_from_reg() local
234 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); in dcn30_get_vco_frequency_from_reg()
235 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; in dcn30_get_vco_frequency_from_reg()
238 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); in dcn30_get_vco_frequency_from_reg()
240 return dc_fixpt_floor(pll_req); in dcn30_get_vco_frequency_from_reg()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c254 struct fixed31_32 pll_req; in get_vco_frequency_from_reg() local
266 pll_req = dc_fixpt_from_int(fbmult_int_val); in get_vco_frequency_from_reg()
272 pll_req.value |= fbmult_frac_val << 16; in get_vco_frequency_from_reg()
275 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); in get_vco_frequency_from_reg()
278 return dc_fixpt_floor(pll_req); in get_vco_frequency_from_reg()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c188 struct fixed31_32 pll_req; in get_vco_frequency_from_reg() local
201 pll_req = dc_fixpt_from_int(fbmult_int_val); in get_vco_frequency_from_reg()
207 pll_req.value |= fbmult_frac_val << 16; in get_vco_frequency_from_reg()
210 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); in get_vco_frequency_from_reg()
213 return dc_fixpt_floor(pll_req); in get_vco_frequency_from_reg()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c250 struct fixed31_32 pll_req; in get_vco_frequency_from_reg() local
263 pll_req = dc_fixpt_from_int(fbmult_int_val); in get_vco_frequency_from_reg()
269 pll_req.value |= fbmult_frac_val << 16; in get_vco_frequency_from_reg()
272 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); in get_vco_frequency_from_reg()
275 return dc_fixpt_floor(pll_req); in get_vco_frequency_from_reg()