| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | gm200.c | 82 pmu_load(struct nv50_devinit *init, u8 type, bool post, in pmu_load() argument
92 if (!post) in pmu_load()
109 gm200_devinit_preos(struct nv50_devinit *init, bool post) in gm200_devinit_preos() argument
114 pmu_load(init, 0x01, post, NULL, NULL); in gm200_devinit_preos()
118 gm200_devinit_post(struct nvkm_devinit *base, bool post) in gm200_devinit_post() argument
135 ret = pmu_load(init, 0x04, post, &exec, &args); in gm200_devinit_post()
142 if (post) { in gm200_devinit_post()
150 if (post) { in gm200_devinit_post()
158 if (post) { in gm200_devinit_post()
168 gm200_devinit_preos(init, post); in gm200_devinit_post()
[all …]
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| D | base.c | 62 if (init && init->func->post) in nvkm_devinit_post()
63 ret = init->func->post(init, init->post); in nvkm_devinit_post()
74 init->post = true; in nvkm_devinit_fini()
88 init->post = init->force_post; in nvkm_devinit_preinit()
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| D | nv50.c | 103 if (!base->post) { in nv50_devinit_preinit()
106 base->post = true; in nv50_devinit_preinit()
112 if (!base->post) { in nv50_devinit_preinit()
116 base->post = true; in nv50_devinit_preinit()
137 while (init->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) { in nv50_devinit_init()
168 .post = nv04_devinit_post,
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| D | tu102.c | 86 tu102_devinit_post(struct nvkm_devinit *base, bool post) in tu102_devinit_post() argument
95 gm200_devinit_preos(init, post); in tu102_devinit_post()
102 .post = tu102_devinit_post,
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| D | priv.h | 11 int (*post)(struct nvkm_devinit *, bool post); member
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| D | gf100.c | 104 base->post = ((nvkm_rd32(device, 0x2240c) & BIT(1)) == 0); in gf100_devinit_preinit()
111 .post = nv04_devinit_post,
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| D | nv1a.c | 33 .post = nv04_devinit_post,
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| D | nv04.c | 414 if (!init->base.post) { in nv04_devinit_preinit()
422 init->base.post = true; in nv04_devinit_preinit()
455 .post = nv04_devinit_post,
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| D | gm107.c | 51 .post = nv04_devinit_post,
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| D | mcp89.c | 58 .post = nv04_devinit_post,
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| D | g98.c | 57 .post = nv04_devinit_post,
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| D | g84.c | 58 .post = nv04_devinit_post,
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| D | nv20.c | 69 .post = nv04_devinit_post,
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| D | ga100.c | 68 .post = tu102_devinit_post,
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| D | gv100.c | 69 .post = gm200_devinit_post,
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| /drivers/video/fbdev/matrox/ |
| D | matroxfb_misc.h | 9 unsigned int* in, unsigned int* feed, unsigned int* post);
13 unsigned int *post) in PLL_calcclock() argument
15 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post); in PLL_calcclock()
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| D | matroxfb_maven.c | 227 unsigned int* in, unsigned int* feed, unsigned int* post, in matroxfb_PLL_mavenclock() argument
283 *post = p; in matroxfb_PLL_mavenclock()
294 dprintk(KERN_ERR "clk: %02X %02X %02X %d %d\n", *in, *feed, *post, fxtal, fwant); in matroxfb_PLL_mavenclock()
300 unsigned int* in, unsigned int* feed, unsigned int* post, in matroxfb_mavenclock() argument
317 *post = p; in matroxfb_mavenclock()
322 unsigned int* in, unsigned int* feed, unsigned int* post) { in DAC1064_calcclock() argument
336 *post = p; in DAC1064_calcclock()
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| /drivers/scsi/aacraid/ |
| D | rx.c | 347 } * post; in aac_rx_check_health() local
358 post = dma_alloc_coherent(&dev->pdev->dev, in aac_rx_check_health()
361 if (unlikely(post == NULL)) { in aac_rx_check_health()
366 post->Post_Command = cpu_to_le32(COMMAND_POST_RESULTS); in aac_rx_check_health()
367 post->Post_Address = cpu_to_le32(baddr); in aac_rx_check_health()
372 post, paddr); in aac_rx_check_health()
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| /drivers/spi/ |
| D | spi-imx.c | 451 unsigned int pre, post; in mx51_ecspi_clkdiv() local
456 post = fls(fin) - fls(fspi); in mx51_ecspi_clkdiv()
457 if (fin > fspi << post) in mx51_ecspi_clkdiv()
458 post++; in mx51_ecspi_clkdiv()
462 post = max(4U, post) - 4; in mx51_ecspi_clkdiv()
463 if (unlikely(post > 0xf)) { in mx51_ecspi_clkdiv()
469 pre = DIV_ROUND_UP(fin, fspi << post) - 1; in mx51_ecspi_clkdiv()
472 __func__, fin, fspi, post, pre); in mx51_ecspi_clkdiv()
475 *fres = (fin / (pre + 1)) >> post; in mx51_ecspi_clkdiv()
478 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); in mx51_ecspi_clkdiv()
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| /drivers/scsi/be2iscsi/ |
| D | be_cmds.c | 1619 u32 loop, post, rdy = 0; in beiscsi_check_fw_rdy() local
1623 post = beiscsi_get_post_stage(phba); in beiscsi_check_fw_rdy()
1624 if (post & POST_ERROR_BIT) in beiscsi_check_fw_rdy()
1626 if ((post & POST_STAGE_MASK) == POST_STAGE_ARMFW_RDY) { in beiscsi_check_fw_rdy()
1635 "BC_%d : FW not ready 0x%x\n", post); in beiscsi_check_fw_rdy()
1849 u32 post, status; in beiscsi_detect_tpe() local
1852 post = beiscsi_get_post_stage(phba); in beiscsi_detect_tpe()
1853 status = post & POST_STAGE_MASK; in beiscsi_detect_tpe()
1858 "BC_%d : HBA error recoverable: 0x%x\n", post); in beiscsi_detect_tpe()
1862 "BC_%d : HBA in UE: 0x%x\n", post); in beiscsi_detect_tpe()
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| /drivers/tty/serial/8250/ |
| D | serial_cs.c | 78 int (*post)(struct pcmcia_device *); member
203 .post = quirk_post_ibm,
676 if (info->quirk && info->quirk->post) in serial_config()
677 if (info->quirk->post(link)) in serial_config()
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| /drivers/infiniband/sw/rxe/ |
| D | rxe_comp.c | 422 bool post; in do_complete() local
425 post = ((qp->sq_sig_type == IB_SIGNAL_ALL_WR) || in do_complete()
429 if (post) in do_complete()
434 if (post) in do_complete()
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| /drivers/gpu/drm/i915/gt/ |
| D | gen2_engine_cs.c | 143 int flush, int post) in __gen2_emit_breadcrumb() argument
156 while (post--) { in __gen2_emit_breadcrumb()
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| /drivers/parport/ |
| D | TODO-parport | 12 b) Handle status readback automatically. IEEE1284 printers can post status
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| D | devinit.h | 10 bool post; member
|