| /drivers/gpu/drm/bridge/analogix/ |
| D | anx7625.c | 292 u8 *post_divider) in anx7625_calculate_m_n() argument
310 for (*post_divider = 1; in anx7625_calculate_m_n()
311 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) in anx7625_calculate_m_n()
312 *post_divider += 1; in anx7625_calculate_m_n()
314 if (*post_divider > POST_DIVIDER_MAX) { in anx7625_calculate_m_n()
315 for (*post_divider = 1; in anx7625_calculate_m_n()
317 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) in anx7625_calculate_m_n()
318 *post_divider += 1; in anx7625_calculate_m_n()
320 if (*post_divider > POST_DIVIDER_MAX) { in anx7625_calculate_m_n()
322 *post_divider); in anx7625_calculate_m_n()
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| /drivers/gpu/drm/radeon/ |
| D | rv730_dpm.c | 50 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local
62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
65 post_divider = 1; in rv730_populate_sclk_value()
67 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
90 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
129 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local
140 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
143 post_divider = 1; in rv730_populate_mclk_value()
165 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
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| D | rv6xx_dpm.c | 150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
152 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()
154 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()
173 if (step->post_divider == 1) in rv6xx_output_stepping()
176 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()
177 u32 hi_len = step->post_divider - 2 - lo_len; in rv6xx_output_stepping()
199 next.post_divider = cur->post_divider; in rv6xx_next_vco_step()
213 return (cur->post_divider > target->post_divider) && in rv6xx_can_step_post_div()
214 ((cur->vco_frequency * target->post_divider) <= in rv6xx_can_step_post_div()
215 (target->vco_frequency * (cur->post_divider - 1))); in rv6xx_can_step_post_div()
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| D | rv6xx_dpm.h | 34 u32 post_divider; member
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| D | radeon_legacy_crtc.c | 742 uint32_t post_divider = 0; in radeon_set_pll() local
820 &reference_div, &post_divider); in radeon_set_pll()
823 if (post_div->divider == post_divider) in radeon_set_pll()
834 post_divider); in radeon_set_pll()
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| D | rv770_dpm.c | 326 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local
334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
338 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()
503 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local
515 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()
517 post_divider = 1; in rv770_populate_sclk_value()
519 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
541 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
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| D | ci_dpm.c | 2637 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2645 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2678 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2711 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2743 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
2982 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
3174 sclk->SclkDid = (u8)dividers.post_divider; in ci_calculate_sclk_params()
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| D | radeon_mode.h | 600 u32 post_divider; member
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| D | radeon_atombios.c | 2923 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in radeon_atom_get_clock_dividers()
2940 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in radeon_atom_get_clock_dividers()
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| D | cik.c | 9421 tmp |= dividers.post_divider; in cik_set_uvd_clock()
9468 tmp |= dividers.post_divider; in cik_set_vce_clocks()
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| /drivers/video/fbdev/aty/ |
| D | mach64_gx.c | 346 u32 post_divider; in aty_var_to_pll_18818() local
352 post_divider = 1; in aty_var_to_pll_18818()
363 post_divider *= 2; in aty_var_to_pll_18818()
374 switch (post_divider) { in aty_var_to_pll_18818()
394 pll->ics2595.post_divider = post_divider; in aty_var_to_pll_18818()
560 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()
678 pll->ics2595.post_divider = 0; in aty_var_to_pll_8398()
796 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_408()
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| D | radeon_monitor.c | 200 rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48); in radeon_get_panel_info_BIOS()
207 pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider); in radeon_get_panel_info_BIOS()
669 rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7; in radeon_fixup_panel_info()
675 (rinfo->panel_info.post_divider << 16), in radeon_fixup_panel_info()
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| D | atyfb.h | 79 u32 post_divider; member
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| D | radeonfb.h | 265 int post_divider; member
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| D | aty128fb.c | 424 u32 post_divider; member
1343 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1381 pll->post_divider = post_dividers[i]; in aty128_var_to_pll()
1397 "vclk_per: %d\n", pll->post_divider, in aty128_var_to_pll()
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| D | radeon_base.c | 1699 (rinfo->panel_info.post_divider << 16); in radeonfb_set_par()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.c | 138 uint32_t post_divider, in calculate_fb_and_fractional_fb_divider() argument
145 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; in calculate_fb_and_fractional_fb_divider()
197 uint32_t post_divider, in calc_fb_divider_checking_tolerance() argument
210 post_divider, in calc_fb_divider_checking_tolerance()
221 ref_divider * post_divider * in calc_fb_divider_checking_tolerance()
239 pll_settings->pix_clk_post_divider = post_divider; in calc_fb_divider_checking_tolerance()
243 div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); in calc_fb_divider_checking_tolerance()
259 uint32_t post_divider; in calc_pll_dividers_in_range() local
270 post_divider = max_post_divider; in calc_pll_dividers_in_range()
271 post_divider >= min_post_divider; in calc_pll_dividers_in_range()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.h | 49 u32 post_divider; member
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| D | cik.c | 1467 tmp |= dividers.post_divider; in cik_set_uvd_clock()
1516 tmp |= dividers.post_divider; in cik_set_vce_clocks()
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| D | vi.c | 1006 tmp |= dividers.post_divider; in vi_set_uvd_clock()
1096 tmp |= dividers.post_divider; in vi_set_vce_clocks()
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| D | amdgpu_atombios.c | 1061 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1078 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
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