| /drivers/gpu/drm/i915/display/ |
| D | intel_psr.c | 91 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr_global_enabled()
103 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr2_global_enabled()
126 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); in psr_irq_control()
128 trans_shift = intel_dp->psr.transcoder; in psr_irq_control()
133 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) in psr_irq_control()
184 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_irq_handler()
192 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); in intel_psr_irq_handler()
194 trans_shift = intel_dp->psr.transcoder; in intel_psr_irq_handler()
199 intel_dp->psr.last_entry_attempt = time_ns; in intel_psr_irq_handler()
206 intel_dp->psr.last_exit = time_ns; in intel_psr_irq_handler()
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| D | intel_bios.c | 735 i915->vbt.psr.enable = driver->psr_enabled; in parse_driver_features()
753 i915->vbt.psr.enable = power->psr & BIT(panel_type); in parse_power_conservation_features()
886 const struct bdb_psr *psr; in parse_psr() local
890 psr = find_section(bdb, BDB_PSR); in parse_psr()
891 if (!psr) { in parse_psr()
896 psr_table = &psr->psr_table[panel_type]; in parse_psr()
898 i915->vbt.psr.full_link = psr_table->full_link; in parse_psr()
899 i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; in parse_psr()
902 i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : in parse_psr()
907 i915->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; in parse_psr()
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| D | intel_display_debugfs.c | 290 if (intel_dp->psr.psr2_enabled) { in psr_source_status()
305 EDP_PSR2_STATUS(intel_dp->psr.transcoder)); in psr_source_status()
322 EDP_PSR_STATUS(intel_dp->psr.transcoder)); in psr_source_status()
335 struct intel_psr *psr = &intel_dp->psr; in intel_psr_status() local
341 seq_printf(m, "Sink support: %s", yesno(psr->sink_support)); in intel_psr_status()
342 if (psr->sink_support) in intel_psr_status()
346 if (!psr->sink_support) in intel_psr_status()
350 mutex_lock(&psr->lock); in intel_psr_status()
352 if (psr->enabled) in intel_psr_status()
353 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; in intel_psr_status()
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| D | intel_display_types.h | 1643 struct intel_psr psr; member
1903 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
1904 (intel_dp)->psr.source_support)
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| D | intel_vbt_defs.h | 851 u16 psr; member
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| /drivers/cpufreq/ |
| D | maple-cpufreq.c | 94 unsigned long psr = scom970_read(SCOM_PSR); in maple_scom_switch_freq() local
96 if ((psr & PSR_CMD_RECEIVED) == 0 && in maple_scom_switch_freq()
97 (((psr >> PSR_CUR_SPEED_SHIFT) ^ in maple_scom_switch_freq()
101 if (psr & PSR_CMD_COMPLETED) in maple_scom_switch_freq()
116 unsigned long psr = scom970_read(SCOM_PSR); in maple_scom_query_freq() local
120 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^ in maple_scom_query_freq()
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| D | pmac64-cpufreq.c | 168 unsigned long psr = scom970_read(SCOM_PSR); in g5_scom_switch_freq() local
170 if ((psr & PSR_CMD_RECEIVED) == 0 && in g5_scom_switch_freq()
171 (((psr >> PSR_CUR_SPEED_SHIFT) ^ in g5_scom_switch_freq()
175 if (psr & PSR_CMD_COMPLETED) in g5_scom_switch_freq()
194 unsigned long psr = scom970_read(SCOM_PSR); in g5_scom_query_freq() local
198 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^ in g5_scom_query_freq()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dmub_psr.c | 364 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx) in dmub_psr_construct() argument
366 psr->ctx = ctx; in dmub_psr_construct()
367 psr->funcs = &psr_funcs; in dmub_psr_construct()
375 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL); in dmub_psr_create() local
377 if (psr == NULL) { in dmub_psr_create()
382 dmub_psr_construct(psr, ctx); in dmub_psr_create()
384 return psr; in dmub_psr_create()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link.c | 2666 struct dmub_psr *psr = dc->res_pool->psr; in dc_link_set_psr_allow_active() local
2669 if (psr == NULL && force_static) in dc_link_set_psr_allow_active()
2681 if (psr != NULL && link->psr_settings.psr_feature_enabled) { in dc_link_set_psr_allow_active()
2682 if (force_static && psr->funcs->psr_force_static) in dc_link_set_psr_allow_active()
2683 psr->funcs->psr_force_static(psr, panel_inst); in dc_link_set_psr_allow_active()
2684 psr->funcs->psr_enable(psr, allow_active, wait, panel_inst); in dc_link_set_psr_allow_active()
2697 struct dmub_psr *psr = dc->res_pool->psr; in dc_link_get_psr_state() local
2703 if (psr != NULL && link->psr_settings.psr_feature_enabled) in dc_link_get_psr_state()
2704 psr->funcs->psr_get_state(psr, state, panel_inst); in dc_link_get_psr_state()
2752 struct dmub_psr *psr; in dc_link_setup_psr() local
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| /drivers/net/can/m_can/ |
| D | m_can.c | 791 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) in m_can_handle_state_errors() argument
796 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { in m_can_handle_state_errors()
802 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { in m_can_handle_state_errors()
808 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { in m_can_handle_state_errors()
831 static inline bool is_lec_err(u32 psr) in is_lec_err() argument
833 psr &= LEC_UNUSED; in is_lec_err()
835 return psr && (psr != LEC_UNUSED); in is_lec_err()
881 u32 psr) in m_can_handle_bus_errors() argument
891 is_lec_err(psr)) in m_can_handle_bus_errors()
892 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); in m_can_handle_bus_errors()
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| /drivers/spi/ |
| D | spi-s3c64xx.c | 874 u32 psr, speed; in s3c64xx_spi_setup() local
882 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; in s3c64xx_spi_setup()
883 psr &= S3C64XX_SPI_PSR_MASK; in s3c64xx_spi_setup()
884 if (psr == S3C64XX_SPI_PSR_MASK) in s3c64xx_spi_setup()
885 psr--; in s3c64xx_spi_setup()
887 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); in s3c64xx_spi_setup()
889 if (psr+1 < S3C64XX_SPI_PSR_MASK) { in s3c64xx_spi_setup()
890 psr++; in s3c64xx_spi_setup()
897 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); in s3c64xx_spi_setup()
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| /drivers/net/wan/ |
| D | n2.c | 145 u8 psr = inb(card->io + N2_PSR); in openwin() local
147 outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR); in openwin()
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| /drivers/media/common/saa7146/ |
| D | saa7146_core.c | 321 u32 psr = saa7146_read(dev, PSR); in interrupt_hw() local
324 dev->name, isr, psr, ssr); in interrupt_hw()
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 1246 if (pool->psr != NULL) in dcn302_resource_destruct()
1247 dmub_psr_destroy(&pool->psr); in dcn302_resource_destruct()
1676 pool->psr = dmub_psr_create(ctx); in dcn302_resource_construct()
1677 if (pool->psr == NULL) { in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 1172 if (pool->psr != NULL) in dcn303_resource_destruct()
1173 dmub_psr_destroy(&pool->psr); in dcn303_resource_destruct()
1607 pool->psr = dmub_psr_create(ctx); in dcn303_resource_construct()
1608 if (pool->psr == NULL) { in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 279 struct dmub_psr *psr; member
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 1023 if (pool->base.psr != NULL) in dcn21_resource_destruct()
1024 dmub_psr_destroy(&pool->base.psr); in dcn21_resource_destruct()
2107 pool->base.psr = dmub_psr_create(ctx); in dcn21_resource_construct()
2109 if (pool->base.psr == NULL) { in dcn21_resource_construct()
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| /drivers/net/ethernet/agere/ |
| D | et131x.c | 2186 struct pkt_stat_desc *psr; in nic_rx_pkts() local
2210 psr = (struct pkt_stat_desc *)(rx_local->ps_ring_virtaddr) + in nic_rx_pkts()
2216 len = psr->word1 & 0xFFFF; in nic_rx_pkts()
2217 ring_index = (psr->word1 >> 26) & 0x03; in nic_rx_pkts()
2219 buff_index = (psr->word1 >> 16) & 0x3FF; in nic_rx_pkts()
2220 word0 = psr->word0; in nic_rx_pkts()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1454 if (pool->base.psr != NULL) in dcn31_resource_destruct()
1455 dmub_psr_destroy(&pool->base.psr); in dcn31_resource_destruct()
2198 pool->base.psr = dmub_psr_create(ctx); in dcn31_resource_construct()
2199 if (pool->base.psr == NULL) { in dcn31_resource_construct()
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| /drivers/net/ethernet/renesas/ |
| D | ravb_main.c | 748 u32 ecsr, psr; in ravb_emac_interrupt_unlocked() local
761 psr = ravb_read(ndev, PSR); in ravb_emac_interrupt_unlocked()
763 psr ^= PSR_LMON; in ravb_emac_interrupt_unlocked()
764 if (!(psr & PSR_LMON)) { in ravb_emac_interrupt_unlocked()
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| /drivers/staging/rtl8723bs/os_dep/ |
| D | ioctl_cfg80211.c | 243 u8 *psr = NULL, sr = 0; in rtw_cfg80211_inform_bss() local
253 psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL); in rtw_cfg80211_inform_bss()
261 if (psr) in rtw_cfg80211_inform_bss()
262 *psr = 0; /* clear sr */ in rtw_cfg80211_inform_bss()
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| /drivers/atm/ |
| D | fore200e.h | 775 volatile u32 __iomem * psr; /* address of PCI specific register */ member
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| D | fore200e.c | 452 int irq_posted = readl(fore200e->regs.pca.psr); in fore200e_pca_irq_check()
496 fore200e->regs.pca.psr = fore200e->virt_base + PCA200E_PSR_OFFSET; in fore200e_pca_map()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1327 if (pool->base.psr != NULL) in dcn30_resource_destruct()
1328 dmub_psr_destroy(&pool->base.psr); in dcn30_resource_destruct()
2792 pool->base.psr = dmub_psr_create(ctx); in dcn30_resource_construct()
2794 if (pool->base.psr == NULL) { in dcn30_resource_construct()
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| /drivers/gpu/drm/amd/display/dmub/inc/ |
| D | dmub_cmd.h | 231 uint8_t psr; member
|