| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | sorgm200.c | 27 gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in gm200_sor_dp_drive() argument
34 pu &= 0x0f; in gm200_sor_dp_drive()
39 if ((data[2] & 0x00000f00) < (pu << 8) || ln == 0) in gm200_sor_dp_drive()
40 data[2] = (data[2] & ~0x00000f00) | (pu << 8); in gm200_sor_dp_drive()
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| D | sornv50.c | 47 nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu, in nv50_sor_power() argument
53 const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift; in nv50_sor_power()
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| D | dacnv50.c | 66 nv50_dac_power(struct nvkm_ior *dac, bool normal, bool pu, in nv50_dac_power() argument
72 const u32 state = 0x80000000 | (0x00000040 * ! pu | in nv50_dac_power()
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| D | sorgf119.c | 71 gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in gf119_sor_dp_drive() argument
81 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0) in gf119_sor_dp_drive()
82 data[2] = (data[2] & ~0x0000ff00) | (pu << 8); in gf119_sor_dp_drive()
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| D | piornv50.c | 58 nv50_pior_power(struct nvkm_ior *pior, bool normal, bool pu, in nv50_pior_power() argument
64 const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift; in nv50_pior_power()
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| D | sorg94.c | 58 g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in g94_sor_dp_drive() argument
68 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0) in g94_sor_dp_drive()
69 data[2] = (data[2] & ~0x0000ff00) | (pu << 8); in g94_sor_dp_drive()
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| D | ior.h | 58 void (*power)(struct nvkm_ior *, bool normal, bool pu,
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| /drivers/pinctrl/mediatek/ |
| D | pinctrl-mtk-common-v2.c | 578 int err, pu, pd; in mtk_pinconf_bias_set_pu_pd() local
581 pu = 0; in mtk_pinconf_bias_set_pu_pd()
584 pu = 1; in mtk_pinconf_bias_set_pu_pd()
587 pu = 0; in mtk_pinconf_bias_set_pu_pd()
594 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); in mtk_pinconf_bias_set_pu_pd()
672 int err, pu, pd; in mtk_pinconf_bias_get_pu_pd() local
674 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); in mtk_pinconf_bias_get_pu_pd()
682 if (pu == 0 && pd == 0) { in mtk_pinconf_bias_get_pu_pd()
685 } else if (pu == 1 && pd == 0) { in mtk_pinconf_bias_get_pu_pd()
688 } else if (pu == 0 && pd == 1) { in mtk_pinconf_bias_get_pu_pd()
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| /drivers/pinctrl/ |
| D | pinctrl-st.c | 229 struct regmap_field *alt, *oe, *pu, *od; member
244 const int alt, oe, pu, od, rt; member
346 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
357 .pu = -1, /* Not Available */
387 struct regmap_field *pull_up = pc->pu; in st_pinconf_set_config()
584 if (pc->pu) { in st_pinconf_get_direction()
585 regmap_field_read(pc->pu, &pu_value); in st_pinconf_get_direction()
1155 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); in st_parse_syscfgs()
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| /drivers/regulator/ |
| D | max77620-regulator.c | 170 int pu = rpdata->active_fps_pu_slot; in max77620_regulator_set_fps_slots() local
178 pu = rpdata->suspend_fps_pu_slot; in max77620_regulator_set_fps_slots()
183 if (pu >= 0) { in max77620_regulator_set_fps_slots()
184 val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT); in max77620_regulator_set_fps_slots()
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| /drivers/of/ |
| D | property.c | 527 u32 *pu) in of_prop_next_u32() argument
544 *pu = be32_to_cpup(curv); in of_prop_next_u32()
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| /drivers/pinctrl/bcm/ |
| D | pinctrl-ns2-mux.c | 170 #define NS2_PIN_DESC(p, n, b, o, s, i, pu, d) \ argument
179 .pull_shift = pu, \
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| /drivers/pinctrl/nuvoton/ |
| D | pinctrl-npcm7xx.c | 1723 u32 ie, oe, pu, pd; in npcm7xx_config_get() local
1730 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask; in npcm7xx_config_get()
1733 rc = (!pu && !pd); in npcm7xx_config_get()
1735 rc = (pu && !pd); in npcm7xx_config_get()
1737 rc = (!pu && pd); in npcm7xx_config_get()
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