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Searched refs:quad_part (Results 1 – 25 of 27) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hubp.c55 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; in hubp3_set_vm_system_aperture_settings()
58 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; in hubp3_set_vm_system_aperture_settings()
59 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; in hubp3_set_vm_system_aperture_settings()
62 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); in hubp3_set_vm_system_aperture_settings()
65 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); in hubp3_set_vm_system_aperture_settings()
112 if (address->grph.addr.quad_part == 0) in hubp3_program_surface_flip_and_addr()
119 if (address->grph.meta_addr.quad_part != 0) { in hubp3_program_surface_flip_and_addr()
138 if (address->video_progressive.luma_addr.quad_part == 0 in hubp3_program_surface_flip_and_addr()
139 || address->video_progressive.chroma_addr.quad_part == 0) in hubp3_program_surface_flip_and_addr()
148 if (address->video_progressive.luma_meta_addr.quad_part != 0) { in hubp3_program_surface_flip_and_addr()
[all …]
Ddcn30_hwseq.c281 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 && in dcn30_mmhubbub_warmup()
286 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part; in dcn30_mmhubbub_warmup()
307 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf]; in dcn30_mmhubbub_warmup()
719 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { in dcn30_program_dmdata_engine()
775 plane->address.grph.cursor_cache_addr.quad_part; in dcn30_apply_idle_power_optimizations()
793 plane->address.page_table_base.quad_part == 0 && in dcn30_apply_idle_power_optimizations()
880 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part; in dcn30_apply_idle_power_optimizations()
881 cmd.mall.cursor_copy_dst.quad_part = in dcn30_apply_idle_power_optimizations()
882 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047; in dcn30_apply_idle_power_optimizations()
892 cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part; in dcn30_apply_idle_power_optimizations()
Ddcn30_mmhubbub.c80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; in mmhubbub3_warmup_mcif()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.c388 if (address->grph.addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
395 if (address->grph.meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
414 if (address->video_progressive.luma_addr.quad_part == 0 in hubp1_program_surface_flip_and_addr()
415 || address->video_progressive.chroma_addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
424 if (address->video_progressive.luma_meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
459 if (address->grph_stereo.left_addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
461 if (address->grph_stereo.right_addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
474 if (address->grph_stereo.right_meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
484 if (address->grph_stereo.left_meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
752 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp1_is_flip_pending()
[all …]
Ddcn10_hw_sequencer.c2254 apt->sys_default.quad_part = physical_page_number.quad_part << 12; in mmhub_read_vm_system_aperture_settings()
2255 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18; in mmhub_read_vm_system_aperture_settings()
2256 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18; in mmhub_read_vm_system_aperture_settings()
2298 fb_base.quad_part = (uint64_t)fb_base_value << 24; in mmhub_read_vm_context0_settings()
2299 fb_offset.quad_part = (uint64_t)fb_offset_value << 24; in mmhub_read_vm_context0_settings()
2300 vm0->pte_base.quad_part += fb_base.quad_part; in mmhub_read_vm_context0_settings()
2301 vm0->pte_base.quad_part -= fb_offset.quad_part; in mmhub_read_vm_context0_settings()
2684 if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { in dcn10_update_dchubp_dpp()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubp.c237 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; in hubp21_set_vm_system_aperture_settings()
238 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; in hubp21_set_vm_system_aperture_settings()
241 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); in hubp21_set_vm_system_aperture_settings()
244 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); in hubp21_set_vm_system_aperture_settings()
711 if (address->grph.addr.quad_part == 0) { in hubp21_program_surface_flip_and_addr()
716 if (address->grph.meta_addr.quad_part != 0) { in hubp21_program_surface_flip_and_addr()
729 if (address->video_progressive.luma_addr.quad_part == 0 in hubp21_program_surface_flip_and_addr()
730 || address->video_progressive.chroma_addr.quad_part == 0) in hubp21_program_surface_flip_and_addr()
733 if (address->video_progressive.luma_meta_addr.quad_part != 0) { in hubp21_program_surface_flip_and_addr()
758 if (address->grph_stereo.left_addr.quad_part == 0) in hubp21_program_surface_flip_and_addr()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubp.c55 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; in hubp2_set_vm_system_aperture_settings()
58 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; in hubp2_set_vm_system_aperture_settings()
59 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; in hubp2_set_vm_system_aperture_settings()
69 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); in hubp2_set_vm_system_aperture_settings()
72 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); in hubp2_set_vm_system_aperture_settings()
737 if (address->grph.addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
744 if (address->grph.meta_addr.quad_part != 0) { in hubp2_program_surface_flip_and_addr()
763 if (address->video_progressive.luma_addr.quad_part == 0 in hubp2_program_surface_flip_and_addr()
764 || address->video_progressive.chroma_addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
773 if (address->video_progressive.luma_meta_addr.quad_part != 0) { in hubp2_program_surface_flip_and_addr()
[all …]
Ddcn20_hwseq.c1141 apt.sys_default.quad_part = 0; in dcn20_enable_plane()
1143 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; in dcn20_enable_plane()
1144 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; in dcn20_enable_plane()
1505 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { in dcn20_update_dchubp_dpp()
2038 attr.address.quad_part = in dcn20_set_dmdata_attributes()
2039 pipe_ctx->stream->dmdata_address.quad_part; in dcn20_set_dmdata_attributes()
2455 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { in dcn20_program_dmdata_engine()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c474 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0) in dcn31_notify_wm_ranges()
496 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in dcn31_get_dpm_table_from_smu()
654 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn31_clk_mgr_construct()
658 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()
666 &smu_dpm_clks.mc_address.quad_part); in dcn31_clk_mgr_construct()
670 smu_dpm_clks.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()
715 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn31_clk_mgr_construct()
724 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn31_clk_mgr_destroy()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c463 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0) in vg_notify_wm_ranges()
717 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in vg_get_dpm_table_from_smu()
754 &clk_mgr->smu_wm_set.mc_address.quad_part); in vg_clk_mgr_construct()
758 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in vg_clk_mgr_construct()
766 &smu_dpm_clks.mc_address.quad_part); in vg_clk_mgr_construct()
770 smu_dpm_clks.mc_address.quad_part = 0; in vg_clk_mgr_construct()
815 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in vg_clk_mgr_construct()
830 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in vg_clk_mgr_destroy()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_debug.c83 plane_state->address.grph.addr.quad_part, in pre_surface_trace()
84 plane_state->address.grph.meta_addr.quad_part, in pre_surface_trace()
195 update->flip_addr->address.grph.addr.quad_part, in update_surface_trace()
196 update->flip_addr->address.grph.meta_addr.quad_part, in update_surface_trace()
Ddc_stream.c321 if (attributes->address.quad_part == 0) { in dc_stream_set_cursor_attributes()
694 pipe_ctx->stream->dmdata_address.quad_part != 0) { in dc_stream_set_dynamic_metadata()
/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_srv.c491 cw0.offset.quad_part = inst_fb->gpu_addr; in dmub_srv_hw_init()
495 cw1.offset.quad_part = stack_fb->gpu_addr; in dmub_srv_hw_init()
509 cw2.offset.quad_part = data_fb->gpu_addr; in dmub_srv_hw_init()
513 cw3.offset.quad_part = bios_fb->gpu_addr; in dmub_srv_hw_init()
517 cw4.offset.quad_part = mail_fb->gpu_addr; in dmub_srv_hw_init()
533 cw5.offset.quad_part = tracebuff_fb->gpu_addr; in dmub_srv_hw_init()
540 cw6.offset.quad_part = fw_state_fb->gpu_addr; in dmub_srv_hw_init()
Ddmub_dcn30.c84 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn30_translate_addr()
Ddmub_dcn31.c80 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn31_translate_addr()
Ddmub_dcn20.c84 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn20_translate_addr()
/drivers/gpu/drm/amd/display/dc/inc/
Dcompressor.h45 uint64_t quad_part; member
/drivers/gpu/drm/amd/amdkfd/
Dkfd_dbgdev.h185 unsigned long long quad_part; member
Dkfd_dbgdev.c138 addr.quad_part = mem_obj->gpu_addr; in dbgdev_diq_submit_ib()
238 addr.quad_part = 0; in dbgdev_address_watch_set_registers()
250 addr.quad_part = (unsigned long long) adw_info->watch_address[index]; in dbgdev_address_watch_set_registers()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_mem_input.c853 if (address->grph.addr.quad_part == 0) in dce_mi_program_surface_flip_and_addr()
858 if (address->grph_stereo.left_addr.quad_part == 0 || in dce_mi_program_surface_flip_and_addr()
859 address->grph_stereo.right_addr.quad_part == 0) in dce_mi_program_surface_flip_and_addr()
Ddmub_abm.c192 …cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_ad… in dmub_abm_init_config()
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c129 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; in dce60_enable_fbc()
/drivers/gpu/drm/amd/display/dc/
Ddc_hw_types.h56 int64_t quad_part; member
/drivers/gpu/drm/amd/display/dmub/inc/
Ddmub_cmd.h190 uint64_t quad_part; /*<< 64 bit address */ member
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c2002 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; in enable_fbc()

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