| /drivers/gpu/drm/radeon/ |
| D | radeon_object.c | 97 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) in radeon_ttm_placement_from_domain() argument
101 rbo->placement.placement = rbo->placements; in radeon_ttm_placement_from_domain()
102 rbo->placement.busy_placement = rbo->placements; in radeon_ttm_placement_from_domain()
107 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && in radeon_ttm_placement_from_domain()
108 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { in radeon_ttm_placement_from_domain()
109 rbo->placements[c].fpfn = in radeon_ttm_placement_from_domain()
110 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_ttm_placement_from_domain()
111 rbo->placements[c].mem_type = TTM_PL_VRAM; in radeon_ttm_placement_from_domain()
112 rbo->placements[c++].flags = 0; in radeon_ttm_placement_from_domain()
115 rbo->placements[c].fpfn = 0; in radeon_ttm_placement_from_domain()
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| D | radeon_fb.c | 114 struct radeon_bo *rbo = gem_to_radeon_bo(gobj); in radeonfb_destroy_pinned_object() local
117 ret = radeon_bo_reserve(rbo, false); in radeonfb_destroy_pinned_object()
119 radeon_bo_kunmap(rbo); in radeonfb_destroy_pinned_object()
120 radeon_bo_unpin(rbo); in radeonfb_destroy_pinned_object()
121 radeon_bo_unreserve(rbo); in radeonfb_destroy_pinned_object()
133 struct radeon_bo *rbo = NULL; in radeonfb_create_pinned_object() local
159 rbo = gem_to_radeon_bo(gobj); in radeonfb_create_pinned_object()
178 ret = radeon_bo_set_tiling_flags(rbo, in radeonfb_create_pinned_object()
186 ret = radeon_bo_reserve(rbo, false); in radeonfb_create_pinned_object()
190 ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, in radeonfb_create_pinned_object()
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| D | radeon_gem.c | 197 struct radeon_bo *rbo = gem_to_radeon_bo(obj); in radeon_gem_object_open() local
198 struct radeon_device *rdev = rbo->rdev; in radeon_gem_object_open()
209 r = radeon_bo_reserve(rbo, false); in radeon_gem_object_open()
214 bo_va = radeon_vm_bo_find(vm, rbo); in radeon_gem_object_open()
216 bo_va = radeon_vm_bo_add(rdev, vm, rbo); in radeon_gem_object_open()
220 radeon_bo_unreserve(rbo); in radeon_gem_object_open()
228 struct radeon_bo *rbo = gem_to_radeon_bo(obj); in radeon_gem_object_close() local
229 struct radeon_device *rdev = rbo->rdev; in radeon_gem_object_close()
240 r = radeon_bo_reserve(rbo, true); in radeon_gem_object_close()
246 bo_va = radeon_vm_bo_find(vm, rbo); in radeon_gem_object_close()
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| D | radeon_ttm.c | 92 struct radeon_bo *rbo; in radeon_evict_flags() local
101 rbo = container_of(bo, struct radeon_bo, tbo); in radeon_evict_flags()
104 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) in radeon_evict_flags()
105 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); in radeon_evict_flags()
106 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && in radeon_evict_flags()
107 bo->resource->start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { in radeon_evict_flags()
108 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_evict_flags()
116 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | in radeon_evict_flags()
118 rbo->placement.num_busy_placement = 0; in radeon_evict_flags()
119 for (i = 0; i < rbo->placement.num_placement; i++) { in radeon_evict_flags()
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| D | radeon_legacy_crtc.c | 382 struct radeon_bo *rbo; in radeon_crtc_do_set_base() local
425 rbo = gem_to_radeon_bo(obj); in radeon_crtc_do_set_base()
427 r = radeon_bo_reserve(rbo, false); in radeon_crtc_do_set_base()
431 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, in radeon_crtc_do_set_base()
434 radeon_bo_unreserve(rbo); in radeon_crtc_do_set_base()
454 nsize = radeon_bo_size(rbo); in radeon_crtc_do_set_base()
464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
465 radeon_bo_unreserve(rbo); in radeon_crtc_do_set_base()
559 rbo = gem_to_radeon_bo(fb->obj[0]); in radeon_crtc_do_set_base()
560 r = radeon_bo_reserve(rbo, false); in radeon_crtc_do_set_base()
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| D | atombios_crtc.c | 1152 struct radeon_bo *rbo; in dce4_crtc_do_set_base() local
1176 rbo = gem_to_radeon_bo(obj); in dce4_crtc_do_set_base()
1177 r = radeon_bo_reserve(rbo, false); in dce4_crtc_do_set_base()
1182 fb_location = radeon_bo_gpu_offset(rbo); in dce4_crtc_do_set_base()
1184 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); in dce4_crtc_do_set_base()
1186 radeon_bo_unreserve(rbo); in dce4_crtc_do_set_base()
1191 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1192 radeon_bo_unreserve(rbo); in dce4_crtc_do_set_base()
1450 rbo = gem_to_radeon_bo(fb->obj[0]); in dce4_crtc_do_set_base()
1451 r = radeon_bo_reserve(rbo, false); in dce4_crtc_do_set_base()
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| D | radeon_uvd.c | 304 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, in radeon_uvd_force_into_uvd_segment() argument
309 for (i = 0; i < rbo->placement.num_placement; ++i) { in radeon_uvd_force_into_uvd_segment()
310 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; in radeon_uvd_force_into_uvd_segment()
311 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; in radeon_uvd_force_into_uvd_segment()
319 if (rbo->placement.num_placement > 1) in radeon_uvd_force_into_uvd_segment()
323 rbo->placements[1] = rbo->placements[0]; in radeon_uvd_force_into_uvd_segment()
324 rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; in radeon_uvd_force_into_uvd_segment()
325 rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; in radeon_uvd_force_into_uvd_segment()
326 rbo->placement.num_placement++; in radeon_uvd_force_into_uvd_segment()
327 rbo->placement.num_busy_placement++; in radeon_uvd_force_into_uvd_segment()
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| D | radeon.h | 1725 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
2844 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_vkms.c | 306 struct amdgpu_bo *rbo; in amdgpu_vkms_prepare_fb() local
319 rbo = gem_to_amdgpu_bo(obj); in amdgpu_vkms_prepare_fb()
320 adev = amdgpu_ttm_adev(rbo->tbo.bdev); in amdgpu_vkms_prepare_fb()
323 tv.bo = &rbo->tbo; in amdgpu_vkms_prepare_fb()
334 domain = amdgpu_display_supported_domains(adev, rbo->flags); in amdgpu_vkms_prepare_fb()
338 r = amdgpu_bo_pin(rbo, domain); in amdgpu_vkms_prepare_fb()
346 r = amdgpu_ttm_alloc_gart(&rbo->tbo); in amdgpu_vkms_prepare_fb()
348 amdgpu_bo_unpin(rbo); in amdgpu_vkms_prepare_fb()
350 DRM_ERROR("%p bind failed\n", rbo); in amdgpu_vkms_prepare_fb()
356 afb->address = amdgpu_bo_gpu_offset(rbo); in amdgpu_vkms_prepare_fb()
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| D | amdgpu_display.c | 637 struct amdgpu_bo *rbo; in extract_render_dcc_offset() local
642 rbo = gem_to_amdgpu_bo(obj); in extract_render_dcc_offset()
643 r = amdgpu_bo_reserve(rbo, false); in extract_render_dcc_offset()
652 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL); in extract_render_dcc_offset()
653 amdgpu_bo_unreserve(rbo); in extract_render_dcc_offset()
1033 struct amdgpu_bo *rbo; in amdgpu_display_get_fb_info() local
1042 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); in amdgpu_display_get_fb_info()
1043 r = amdgpu_bo_reserve(rbo, false); in amdgpu_display_get_fb_info()
1053 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); in amdgpu_display_get_fb_info()
1056 *tmz_surface = amdgpu_bo_encrypted(rbo); in amdgpu_display_get_fb_info()
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| /drivers/gpu/drm/qxl/ |
| D | qxl_release.c | 284 struct qxl_bo **rbo) in qxl_alloc_release_reserved() argument
310 if (rbo) in qxl_alloc_release_reserved()
311 *rbo = NULL; in qxl_alloc_release_reserved()
341 if (rbo) in qxl_alloc_release_reserved()
342 *rbo = bo; in qxl_alloc_release_reserved()
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| D | qxl_drv.h | 390 struct qxl_bo **rbo);
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 7434 struct amdgpu_bo *rbo; in dm_plane_helper_prepare_fb() local
7449 rbo = gem_to_amdgpu_bo(obj); in dm_plane_helper_prepare_fb()
7450 adev = amdgpu_ttm_adev(rbo->tbo.bdev); in dm_plane_helper_prepare_fb()
7453 tv.bo = &rbo->tbo; in dm_plane_helper_prepare_fb()
7464 domain = amdgpu_display_supported_domains(adev, rbo->flags); in dm_plane_helper_prepare_fb()
7468 r = amdgpu_bo_pin(rbo, domain); in dm_plane_helper_prepare_fb()
7476 r = amdgpu_ttm_alloc_gart(&rbo->tbo); in dm_plane_helper_prepare_fb()
7478 amdgpu_bo_unpin(rbo); in dm_plane_helper_prepare_fb()
7480 DRM_ERROR("%p bind failed\n", rbo); in dm_plane_helper_prepare_fb()
7486 afb->address = amdgpu_bo_gpu_offset(rbo); in dm_plane_helper_prepare_fb()
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