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Searched refs:read_reg (Results 1 – 25 of 131) sorted by relevance

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/drivers/net/can/sja1000/
Dsja1000.c95 priv->read_reg(priv, SJA1000_SR); in sja1000_write_cmdreg()
101 return (priv->read_reg(priv, SJA1000_MOD) == 0xFF); in sja1000_is_absent()
118 unsigned char status = priv->read_reg(priv, SJA1000_MOD); in set_reset_mode()
134 status = priv->read_reg(priv, SJA1000_MOD); in set_reset_mode()
143 unsigned char status = priv->read_reg(priv, SJA1000_MOD); in set_normal_mode()
169 status = priv->read_reg(priv, SJA1000_MOD); in set_normal_mode()
213 if (!(priv->read_reg(priv, SJA1000_CDR) & CDR_PELICAN)) in sja1000_start()
219 priv->read_reg(priv, SJA1000_ECC); in sja1000_start()
222 priv->read_reg(priv, SJA1000_IR); in sja1000_start()
269 bec->txerr = priv->read_reg(priv, SJA1000_TXERR); in sja1000_get_berr_counter()
[all …]
Dsja1000_platform.c102 priv->read_reg = sp_technologic_read_reg16; in sp_technologic_init()
120 priv->read_reg = sp_read_reg32; in sp_populate()
124 priv->read_reg = sp_read_reg16; in sp_populate()
129 priv->read_reg = sp_read_reg8; in sp_populate()
146 priv->read_reg = sp_read_reg32; in sp_populate_of()
150 priv->read_reg = sp_read_reg16; in sp_populate_of()
155 priv->read_reg = sp_read_reg8; in sp_populate_of()
Dplx_pci.c420 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == in plx_pci_check_sja1000()
422 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) && in plx_pci_check_sja1000()
423 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL)) in plx_pci_check_sja1000()
433 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL && in plx_pci_check_sja1000()
434 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL && in plx_pci_check_sja1000()
435 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL) in plx_pci_check_sja1000()
685 priv->read_reg = plx_pci_read_reg; in plx_pci_add_card()
/drivers/media/pci/ivtv/
Divtv-gpio.c101 curout = read_reg(IVTV_REG_GPIO_OUT); in ivtv_reset_ir_gpio()
102 curdir = read_reg(IVTV_REG_GPIO_DIR); in ivtv_reset_ir_gpio()
125 curout = read_reg(IVTV_REG_GPIO_OUT); in ivtv_reset_tuner_gpio()
165 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_clock_freq()
175 if (mask == 0 || (read_reg(IVTV_REG_GPIO_IN) & mask)) in subdev_g_tuner()
206 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_tuner()
218 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_radio()
244 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_audio_routing()
259 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | in subdev_s_ctrl()
272 read_reg(IVTV_REG_GPIO_DIR), read_reg(IVTV_REG_GPIO_OUT), in subdev_log_status()
[all …]
Divtv-yuv.c846 yi->reg_2834 = read_reg(0x02834); in ivtv_yuv_init()
847 yi->reg_2838 = read_reg(0x02838); in ivtv_yuv_init()
848 yi->reg_283c = read_reg(0x0283c); in ivtv_yuv_init()
849 yi->reg_2840 = read_reg(0x02840); in ivtv_yuv_init()
850 yi->reg_2844 = read_reg(0x02844); in ivtv_yuv_init()
851 yi->reg_2848 = read_reg(0x02848); in ivtv_yuv_init()
852 yi->reg_2854 = read_reg(0x02854); in ivtv_yuv_init()
853 yi->reg_285c = read_reg(0x0285c); in ivtv_yuv_init()
854 yi->reg_2864 = read_reg(0x02864); in ivtv_yuv_init()
855 yi->reg_2870 = read_reg(0x02870); in ivtv_yuv_init()
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/drivers/net/ethernet/intel/igb/
De1000_phy.c64 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igb_get_phy_id()
70 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igb_get_phy_id()
475 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); in igb_copper_link_setup_82580()
489 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); in igb_copper_link_setup_82580()
534 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); in igb_copper_link_setup_m88()
583 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, in igb_copper_link_setup_m88()
636 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); in igb_copper_link_setup_m88_gen2()
764 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); in igb_copper_link_setup_igp()
794 ret_val = phy->ops.read_reg(hw, in igb_copper_link_setup_igp()
808 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); in igb_copper_link_setup_igp()
[all …]
/drivers/macintosh/
Dtherm_windtunnel.c138 read_reg( struct i2c_client *cl, int reg, int len ) in read_reg() function
173 temp = read_reg( x.thermostat, 0, 2 ); in poll_temp()
179 casetemp = read_reg(x.fan, 0x0b, 1) << 8; in poll_temp()
180 casetemp |= (read_reg(x.fan, 0x06, 1) & 0x7) << 5; in poll_temp()
215 x.r0 = read_reg( x.fan, 0x00, 1 ); in setup_hardware()
216 x.r1 = read_reg( x.fan, 0x01, 1 ); in setup_hardware()
217 x.r20 = read_reg( x.fan, 0x20, 1 ); in setup_hardware()
218 x.r23 = read_reg( x.fan, 0x23, 1 ); in setup_hardware()
219 x.r25 = read_reg( x.fan, 0x25, 1 ); in setup_hardware()
222 if( (val=read_reg(x.thermostat, 1, 1)) >= 0 ) { in setup_hardware()
[all …]
Dtherm_adt746x.c111 read_reg(struct thermostat* th, int reg) in read_reg() function
134 tmp[1] = read_reg(th, addr); in read_fan_speed()
135 tmp[0] = read_reg(th, addr + 1); in read_fan_speed()
174 manual = read_reg(th, MANUAL_MODE[fan]); in write_fan_speed()
182 manual = read_reg(th, in write_fan_speed()
189 manual = read_reg(th, MANUAL_MODE[fan]); in write_fan_speed()
204 th->temps[i] = read_reg(th, TEMP_REG[i]); in read_sensors()
375 BUILD_SHOW_FUNC_INT(sensor1_temperature, (read_reg(th, TEMP_REG[1])))
376 BUILD_SHOW_FUNC_INT(sensor2_temperature, (read_reg(th, TEMP_REG[2])))
508 rc = read_reg(th, CONFIG_REG); in probe_thermostat()
[all …]
/drivers/mtd/nand/onenand/
Donenand_omap2.c59 static inline unsigned short read_reg(struct omap2_onenand *c, int reg) in read_reg() function
170 intr = read_reg(c, ONENAND_REG_INTERRUPT); in omap2_onenand_wait()
174 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); in omap2_onenand_wait()
188 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1); in omap2_onenand_wait()
193 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1); in omap2_onenand_wait()
199 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); in omap2_onenand_wait()
200 intr = read_reg(c, ONENAND_REG_INTERRUPT); in omap2_onenand_wait()
209 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); in omap2_onenand_wait()
219 intr = read_reg(c, in omap2_onenand_wait()
224 intr = read_reg(c, ONENAND_REG_INTERRUPT); in omap2_onenand_wait()
[all …]
/drivers/gpio/
Dgpio-mmio.c138 return !!(gc->read_reg(gc->reg_set) & pinmask); in bgpio_get_set()
140 return !!(gc->read_reg(gc->reg_dat) & pinmask); in bgpio_get_set()
160 *bits |= gc->read_reg(gc->reg_set) & set_mask; in bgpio_get_set_multiple()
162 *bits |= gc->read_reg(gc->reg_dat) & get_mask; in bgpio_get_set_multiple()
169 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); in bgpio_get()
180 *bits |= gc->read_reg(gc->reg_dat) & *mask; in bgpio_get_multiple()
202 val = gc->read_reg(gc->reg_dat) & readmask; in bgpio_get_multiple_be()
374 if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio)) in bgpio_get_dir()
380 if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio))) in bgpio_get_dir()
425 gc->read_reg = bgpio_read8; in bgpio_setup_accessors()
[all …]
Dgpio-mpc8xxx.c74 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
75 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
120 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) in mpc8xxx_gpio_irq_cascade()
121 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); in mpc8xxx_gpio_irq_cascade()
137 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_unmask()
152 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_mask()
178 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
186 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
219 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
227 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
[all …]
/drivers/net/ethernet/intel/igc/
Digc_phy.c37 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
43 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
74 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_phy_has_link()
85 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_phy_has_link()
113 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); in igc_power_up_phy_copper()
130 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); in igc_power_down_phy_copper()
240 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); in igc_phy_setup_autoneg()
246 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, in igc_phy_setup_autoneg()
254 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << in igc_phy_setup_autoneg()
416 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_wait_autoneg()
[all …]
/drivers/block/paride/
Dpt.c257 static inline int read_reg(struct pi_adapter *pi, int reg) in read_reg() function
283 s = read_reg(pi, 7); in pt_wait()
284 e = read_reg(pi, 1); in pt_wait()
285 p = read_reg(pi, 2); in pt_wait()
318 if (read_reg(pi, 2) != 1) { in pt_command()
337 if (read_reg(pi, 7) & STAT_DRQ) { in pt_completion()
338 n = (((read_reg(pi, 4) + 256 * read_reg(pi, 5)) + in pt_completion()
340 p = read_reg(pi, 2) & 3; in pt_completion()
407 s = read_reg(pi, 7); in pt_poll_dsc()
408 e = read_reg(pi, 1); in pt_poll_dsc()
[all …]
Dpg.c268 static inline int read_reg(struct pg *dev, int reg) in read_reg() function
306 s = read_reg(dev, 7); in pg_wait()
307 e = read_reg(dev, 1); in pg_wait()
308 p = read_reg(dev, 2); in pg_wait()
338 if (read_reg(dev, 2) != 1) { in pg_command()
366 while (read_reg(dev, 7) & STAT_DRQ) { in pg_completion()
367 d = (read_reg(dev, 4) + 256 * read_reg(dev, 5)); in pg_completion()
369 p = read_reg(dev, 2) & 3; in pg_completion()
405 got[i] = read_reg(dev, i + 1); in pg_reset()
Dpcd.c320 static inline int read_reg(struct pcd_unit *cd, int reg) in read_reg() function
340 s = read_reg(cd, 7); in pcd_wait()
341 e = read_reg(cd, 1); in pcd_wait()
342 p = read_reg(cd, 2); in pcd_wait()
374 if (read_reg(cd, 2) != 1) { in pcd_command()
396 while (read_reg(cd, 7) & IDE_DRQ) { in pcd_completion()
397 d = read_reg(cd, 4) + 256 * read_reg(cd, 5); in pcd_completion()
399 p = read_reg(cd, 2) & 3; in pcd_completion()
532 flg &= (read_reg(cd, i + 1) == expect[i]); in pcd_reset()
537 printk("%3x", read_reg(cd, i + 1)); in pcd_reset()
Dpf.c415 static inline int read_reg(struct pf_unit *pf, int reg) in read_reg() function
435 s = read_reg(pf, 7); in pf_wait()
436 e = read_reg(pf, 1); in pf_wait()
437 p = read_reg(pf, 2); in pf_wait()
469 if (read_reg(pf, 2) != 1) { in pf_command()
487 if ((read_reg(pf, 2) & 2) && (read_reg(pf, 7) & STAT_DRQ)) { in pf_completion()
488 n = (((read_reg(pf, 4) + 256 * read_reg(pf, 5)) + in pf_completion()
575 flg &= (read_reg(pf, i + 1) == expect[i]); in pf_reset()
580 printk("%3x", read_reg(pf, i + 1)); in pf_reset()
/drivers/net/can/
Dxilinx_can.c204 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); member
368 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { in set_reset_mode()
401 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_set_bittiming()
443 priv->read_reg(priv, XCAN_BRPR_OFFSET), in xcan_set_bittiming()
444 priv->read_reg(priv, XCAN_BTR_OFFSET)); in xcan_set_bittiming()
508 priv->read_reg(priv, XCAN_SR_OFFSET)); in xcan_chip_start()
648 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_start_xmit_fifo()
681 if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) & in xcan_start_xmit_mailbox()
757 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); in xcan_rx()
758 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >> in xcan_rx()
[all …]
/drivers/media/i2c/
Dtw2804.c125 static int read_reg(struct i2c_client *client, u8 reg, u8 channel) in read_reg() function
171 ctrl->val = read_reg(client, TW2804_REG_GAIN, 0); in tw2804_g_volatile_ctrl()
175 ctrl->val = read_reg(client, TW2804_REG_CHROMA_GAIN, 0); in tw2804_g_volatile_ctrl()
179 ctrl->val = read_reg(client, TW2804_REG_BLUE_BALANCE, 0); in tw2804_g_volatile_ctrl()
183 ctrl->val = read_reg(client, TW2804_REG_RED_BALANCE, 0); in tw2804_g_volatile_ctrl()
199 reg = read_reg(client, addr, state->channel); in tw2804_s_ctrl()
210 reg = read_reg(client, addr, state->channel); in tw2804_s_ctrl()
310 reg = read_reg(client, 0x22, dec->channel); in tw2804_s_video_routing()
/drivers/media/dvb-frontends/
Dstv0910.c173 static int read_reg(struct stv *state, u16 reg, u8 *val) in read_reg() function
191 status = read_reg(state, reg, &tmp); in write_shared_reg()
203 status = read_reg(state, field >> 16, &old); in write_field()
223 read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
486 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3); in get_cur_symbol_rate()
487 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2); in get_cur_symbol_rate()
488 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1); in get_cur_symbol_rate()
489 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0); in get_cur_symbol_rate()
490 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2); in get_cur_symbol_rate()
491 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1); in get_cur_symbol_rate()
[all …]
Dlgdt3305.c151 #define read_reg(state, reg) \ macro
562 gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3); in lgdt3305_sleep()
563 gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4); in lgdt3305_sleep()
994 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) | in lgdt3305_read_snr()
995 (read_reg(state, LGDT3305_PT_MSE_2) << 8) | in lgdt3305_read_snr()
996 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff); in lgdt3305_read_snr()
1001 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) | in lgdt3305_read_snr()
1002 (read_reg(state, LGDT3305_EQ_MSE_2) << 8) | in lgdt3305_read_snr()
1003 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff); in lgdt3305_read_snr()
1009 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) | in lgdt3305_read_snr()
[all …]
/drivers/media/radio/
Dradio-tea5777.c218 tea->read_reg = -1; in radio_tea5777_set_freq()
228 if (tea->read_reg != -1) in radio_tea5777_update_read_reg()
242 res = tea->ops->read_reg(tea, &tea->read_reg); in radio_tea5777_update_read_reg()
306 (tea->read_reg & TEA5777_R_FM_STEREO_MASK)) in vidioc_g_tuner()
312 v->signal = (tea->read_reg & TEA5777_R_LEVEL_MASK) >> in vidioc_g_tuner()
316 tea->read_reg = -1; in vidioc_g_tuner()
459 tea->freq = (tea->read_reg & TEA5777_R_FM_PLL_MASK); in vidioc_s_hw_freq_seek()
462 if ((tea->read_reg & TEA5777_R_SFOUND_MASK)) { in vidioc_s_hw_freq_seek()
467 if (tea->read_reg & TEA5777_R_BLIM_MASK) { in vidioc_s_hw_freq_seek()
473 tea->read_reg = -1; in vidioc_s_hw_freq_seek()
/drivers/net/can/c_can/
Dc_can_main.c228 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; in c_can_irq_control()
244 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) in c_can_obj_update()
401 data = priv->read_reg(priv, dreg); in c_can_read_msg_object()
493 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { in c_can_wait_for_ctrl_init()
527 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); in c_can_set_bittiming()
575 while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) { in c_can_software_reset()
701 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); in __c_can_get_berr_counter()
733 pend = priv->read_reg(priv, C_CAN_INTPND2_REG); in c_can_do_tx()
830 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_NAPI)); in c_can_read_objects()
868 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); in c_can_get_pending()
[all …]
Dc_can_pci.c91 val = priv->read_reg(priv, index); in c_can_pci_read_reg32()
92 val |= ((u32)priv->read_reg(priv, index + 1)) << 16; in c_can_pci_read_reg32()
192 priv->read_reg = c_can_pci_read_reg_aligned_to_32bit; in c_can_pci_probe()
196 priv->read_reg = c_can_pci_read_reg_aligned_to_16bit; in c_can_pci_probe()
200 priv->read_reg = c_can_pci_read_reg_32bit; in c_can_pci_probe()
/drivers/mtd/nand/raw/brcmnand/
Dbrcmnand.h31 u32 (*read_reg)(struct brcmnand_soc *soc, u32 offset); member
76 return soc && soc->ops && soc->ops->read_reg && soc->ops->write_reg; in brcmnand_soc_has_ops()
81 return soc->ops->read_reg(soc, offset); in brcmnand_soc_read()
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x550.c337 hw->phy.ops.read_reg = NULL; in ixgbe_identify_phy_x550em()
537 hw->phy.ops.read_reg = NULL; in ixgbe_identify_phy_fw()
1822 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, in ixgbe_setup_mac_link_sfp_x550a()
1839 ret_val = hw->phy.ops.read_reg(hw, reg_slice, in ixgbe_setup_mac_link_sfp_x550a()
1858 return hw->phy.ops.read_reg(hw, reg_slice, in ixgbe_setup_mac_link_sfp_x550a()
1933 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, in ixgbe_check_link_t_X550em()
2340 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, in ixgbe_get_lasi_ext_t_x550em()
2348 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, in ixgbe_get_lasi_ext_t_x550em()
2357 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, in ixgbe_get_lasi_ext_t_x550em()
2373 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, in ixgbe_get_lasi_ext_t_x550em()
[all …]

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