| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20v2.c | 69 double ref_freq_to_pix_freq,
819 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; in dml20v2_rq_dlg_get_dlg_params() local
927 ASSERT(ref_freq_to_pix_freq < 4.0); in dml20v2_rq_dlg_get_dlg_params()
929 disp_dlg_regs->ref_freq_to_pix_freq = in dml20v2_rq_dlg_get_dlg_params()
930 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); in dml20v2_rq_dlg_get_dlg_params()
931 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal in dml20v2_rq_dlg_get_dlg_params()
935 * (double) ref_freq_to_pix_freq); in dml20v2_rq_dlg_get_dlg_params()
966 ref_freq_to_pix_freq); in dml20v2_rq_dlg_get_dlg_params()
1369 ref_freq_to_pix_freq, in dml20v2_rq_dlg_get_dlg_params()
1385 ref_freq_to_pix_freq, in dml20v2_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20.c | 69 double ref_freq_to_pix_freq,
819 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; in dml20_rq_dlg_get_dlg_params() local
927 ASSERT(ref_freq_to_pix_freq < 4.0); in dml20_rq_dlg_get_dlg_params()
929 disp_dlg_regs->ref_freq_to_pix_freq = in dml20_rq_dlg_get_dlg_params()
930 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); in dml20_rq_dlg_get_dlg_params()
931 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal in dml20_rq_dlg_get_dlg_params()
935 * (double) ref_freq_to_pix_freq); in dml20_rq_dlg_get_dlg_params()
965 ref_freq_to_pix_freq); in dml20_rq_dlg_get_dlg_params()
1368 ref_freq_to_pix_freq, in dml20_rq_dlg_get_dlg_params()
1384 ref_freq_to_pix_freq, in dml20_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 46 double ref_freq_to_pix_freq,
865 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; in dml_rq_dlg_get_dlg_params() local
973 ASSERT(ref_freq_to_pix_freq < 4.0); in dml_rq_dlg_get_dlg_params()
975 disp_dlg_regs->ref_freq_to_pix_freq = in dml_rq_dlg_get_dlg_params()
976 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); in dml_rq_dlg_get_dlg_params()
977 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal in dml_rq_dlg_get_dlg_params()
981 * (double) ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1017 ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1437 ref_freq_to_pix_freq, in dml_rq_dlg_get_dlg_params()
1454 ref_freq_to_pix_freq, in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 895 double ref_freq_to_pix_freq, in calculate_ttu_cursor() argument
937 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq in calculate_ttu_cursor()
948 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq in calculate_ttu_cursor()
1019 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; in dml_rq_dlg_get_dlg_params() local
1132 ASSERT(ref_freq_to_pix_freq < 4.0); in dml_rq_dlg_get_dlg_params()
1134 disp_dlg_regs->ref_freq_to_pix_freq = in dml_rq_dlg_get_dlg_params()
1135 (unsigned int)(ref_freq_to_pix_freq * dml_pow(2, 19)); in dml_rq_dlg_get_dlg_params()
1136 disp_dlg_regs->refcyc_per_htotal = (unsigned int)(ref_freq_to_pix_freq * (double)htotal in dml_rq_dlg_get_dlg_params()
1168 ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1306 disp_dlg_regs->refcyc_h_blank_end = (unsigned int)((double) hblank_end * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_rq_dlg_calc_31.c | 872 double ref_freq_to_pix_freq, in calculate_ttu_cursor() argument
913 …*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width; in calculate_ttu_cursor()
921 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width; in calculate_ttu_cursor()
975 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; in dml_rq_dlg_get_dlg_params() local
1071 …DLG: %s: interlaced = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0); in dml_rq_dlg_get_dlg_params()
1073 disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); in dml_rq_dlg_get_dlg_params()
1074 …disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_po… in dml_rq_dlg_get_dlg_params()
1088 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1199 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
1203 … hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 1022 double ref_freq_to_pix_freq; in dml1_rq_dlg_get_dlg_params() local
1151 ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; in dml1_rq_dlg_get_dlg_params()
1152 ASSERT(ref_freq_to_pix_freq < 4.0); in dml1_rq_dlg_get_dlg_params()
1153 disp_dlg_regs->ref_freq_to_pix_freq = in dml1_rq_dlg_get_dlg_params()
1154 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); in dml1_rq_dlg_get_dlg_params()
1155 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal in dml1_rq_dlg_get_dlg_params()
1158 * (double) ref_freq_to_pix_freq); in dml1_rq_dlg_get_dlg_params()
1193 ref_freq_to_pix_freq); in dml1_rq_dlg_get_dlg_params()
1444 …disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; /* in terms of r… in dml1_rq_dlg_get_dlg_params()
1536 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); in dml1_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_helpers.c | 233 dlg_regs.ref_freq_to_pix_freq); in print__dlg_regs_st()
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| D | display_mode_structs.h | 456 unsigned int ref_freq_to_pix_freq; member
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hubp.c | 366 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); in hubp21_validate_dml_output()
386 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) in hubp21_validate_dml_output()
388 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); in hubp21_validate_dml_output()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubp.c | 102 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); in hubp2_program_deadline()
1118 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); in hubp2_read_state_common()
1406 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); in hubp2_validate_dml_output()
1426 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) in hubp2_validate_dml_output()
1428 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); in hubp2_validate_dml_output()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubp.c | 609 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); in hubp1_program_deadline()
931 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); in hubp1_read_state_common()
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| D | dcn10_hw_sequencer_debug.c | 263 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_get_dlg_states()
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| D | dcn10_hw_sequencer.c | 239 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_log_hubp_states()
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