Home
last modified time | relevance | path

Searched refs:refcyc_per_meta_chunk_vblank_l (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubp.c422 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp21_validate_dml_output()
468 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) in hubp21_validate_dml_output()
470 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp21_validate_dml_output()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubp.c268 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp2_setup_interdependent()
1125 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp2_read_state_common()
1462 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp2_validate_dml_output()
1508 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) in hubp2_validate_dml_output()
1510 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp2_validate_dml_output()
Ddcn20_hwseq.c1360 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || in dcn20_detect_pipe_changes()
1378 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; in dcn20_detect_pipe_changes()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c1506 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml_rq_dlg_get_dlg_params()
1510 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 0; in dml_rq_dlg_get_dlg_params()
1511 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1514 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assig… in dml_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_rq_dlg_helpers.c248 dlg_regs.refcyc_per_meta_chunk_vblank_l); in print__dlg_regs_st()
Ddisplay_mode_structs.h461 unsigned int refcyc_per_meta_chunk_vblank_l; member
Ddml1_display_rq_dlg_calc.c1544 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml1_rq_dlg_get_dlg_params()
1547 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); in dml1_rq_dlg_get_dlg_params()
1550 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assign… in dml1_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20v2.c1423 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml20v2_rq_dlg_get_dlg_params()
1426 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); in dml20v2_rq_dlg_get_dlg_params()
1429 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assig… in dml20v2_rq_dlg_get_dlg_params()
Ddisplay_rq_dlg_calc_20.c1422 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml20_rq_dlg_get_dlg_params()
1425 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); in dml20_rq_dlg_get_dlg_params()
1428 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assig… in dml20_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_rq_dlg_calc_31.c1559 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) ht… in dml_rq_dlg_get_dlg_params()
1560 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1562 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // … in dml_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c1684 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml_rq_dlg_get_dlg_params()
1687 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1690 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assig… in dml_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.c708 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp1_setup_interdependent()
938 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp1_read_state_common()
Ddcn10_hw_sequencer_debug.c265 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_get_dlg_states()
Ddcn10_hw_sequencer.c241 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_log_hubp_states()