/drivers/rtc/ |
D | rtc-aspeed.c | 26 u32 reg1, reg2; in aspeed_rtc_read_time() local 34 reg2 = readl(rtc->base + RTC_YEAR); in aspeed_rtc_read_time() 36 } while (reg2 != readl(rtc->base + RTC_YEAR)); in aspeed_rtc_read_time() 43 cent = (reg2 >> 16) & 0x1f; in aspeed_rtc_read_time() 44 year = (reg2 >> 8) & 0x7f; in aspeed_rtc_read_time() 45 tm->tm_mon = ((reg2 >> 0) & 0x0f) - 1; in aspeed_rtc_read_time() 56 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local 65 reg2 = ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) | in aspeed_rtc_set_time() 72 writel(reg2, rtc->base + RTC_YEAR); in aspeed_rtc_set_time()
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/drivers/media/dvb-frontends/ |
D | tua6100.c | 65 u8 reg2[] = { 0x02, 0x00, 0x00 }; in tua6100_set_params() local 68 struct i2c_msg msg2 = { .addr = priv->i2c_address, .flags = 0, .buf = reg2, .len = 3 }; in tua6100_set_params() 92 reg2[1] = (_R_VAL >> 8) & 0x03; in tua6100_set_params() 93 reg2[2] = _R_VAL; in tua6100_set_params() 95 reg2[1] |= 0x1c; in tua6100_set_params() 97 reg2[1] |= 0x0c; in tua6100_set_params() 99 reg2[1] |= 0x1c; in tua6100_set_params()
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D | s5h1409.c | 556 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode() local 572 reg2 = s5h1409_readreg(state, 0xad); in s5h1409_set_qam_interleave_mode() 576 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); in s5h1409_set_qam_interleave_mode() 594 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode_legacy() local 603 reg2 = s5h1409_readreg(state, 0xad); in s5h1409_set_qam_interleave_mode_legacy() 607 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); in s5h1409_set_qam_interleave_mode_legacy()
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D | si21xx.c | 481 u8 reg2[2]; in si21xx_init() local 513 reg2[0] = in si21xx_init() 519 reg2[1] = 0; in si21xx_init() 524 status |= si21_writeregs(state, TS_CTRL_REG_1, reg2, 0x02); in si21xx_init()
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/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
D | irq_service_dcn21.c | 216 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 224 .ack_reg = SRI(reg2, block, reg_num),\ 226 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 228 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 230 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 238 .ack_reg = SRI_DMUB(reg2),\ 240 reg2 ## __ ## mask2 ## _MASK,\ 242 reg2 ## __ ## mask2 ## _MASK \
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/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
D | irq_service_dcn30.c | 222 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 230 .ack_reg = SRI(reg2, block, reg_num),\ 232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 234 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 236 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 244 .ack_reg = SRI_DMUB(reg2),\ 246 reg2 ## __ ## mask2 ## _MASK,\ 248 reg2 ## __ ## mask2 ## _MASK \
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/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
D | irq_service_dcn302.c | 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 202 .ack_reg = SRI(reg2, block, reg_num),\ 203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 204 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 221 .ack_reg = SRI_DMUB(reg2),\ 223 reg2 ## __ ## mask2 ## _MASK,\ 225 reg2 ## __ ## mask2 ## _MASK \
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/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
D | irq_service_dcn31.c | 209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 217 .ack_reg = SRI(reg2, block, reg_num),\ 219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument 231 .ack_reg = SRI_DMUB(reg2),\ 233 reg2 ## __ ## mask2 ## _MASK,\ 235 reg2 ## __ ## mask2 ## _MASK \
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/drivers/mcb/ |
D | mcb-parse.c | 48 __le32 reg2; in chameleon_parse_gdd() local 55 reg2 = readl(&gdd->reg2); in chameleon_parse_gdd() 62 mdev->bar = GDD_BAR(reg2); in chameleon_parse_gdd() 63 mdev->group = GDD_GRP(reg2); in chameleon_parse_gdd() 64 mdev->inst = GDD_INS(reg2); in chameleon_parse_gdd()
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D | mcb-internal.h | 67 __le32 reg2; member
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/drivers/media/tuners/ |
D | tda827x.c | 241 unsigned char reg2[2]; in tda827xo_set_analog_params() local 279 msg.buf = reg2; in tda827xo_set_analog_params() 281 reg2[0] = 0x80; in tda827xo_set_analog_params() 282 reg2[1] = 0; in tda827xo_set_analog_params() 285 reg2[0] = 0x60; in tda827xo_set_analog_params() 286 reg2[1] = 0xbf; in tda827xo_set_analog_params() 289 reg2[0] = 0x30; in tda827xo_set_analog_params() 290 reg2[1] = tuner_reg[4] + 0x80; in tda827xo_set_analog_params() 294 reg2[0] = 0x30; in tda827xo_set_analog_params() 295 reg2[1] = tuner_reg[4] + 4; in tda827xo_set_analog_params() [all …]
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/drivers/power/supply/ |
D | wm831x_power.c | 260 int ret, reg1, reg2; in wm831x_config_battery() local 271 reg2 = 0; in wm831x_config_battery() 280 reg2 |= WM831X_CHG_OFF_MSK; in wm831x_config_battery() 286 pdata->trickle_ilim, ®2, in wm831x_config_battery() 290 pdata->vsel, ®2, in wm831x_config_battery() 294 pdata->fast_ilim, ®2, in wm831x_config_battery() 302 pdata->timeout, ®2, in wm831x_config_battery() 326 reg2); in wm831x_config_battery()
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/drivers/hwmon/ |
D | nct7904.c | 392 unsigned int reg1, reg2, reg3; in nct7904_read_temp() local 466 reg2 = TEMP_CH1_W_REG; in nct7904_read_temp() 471 reg2 = TEMP_CH1_WH_REG; in nct7904_read_temp() 476 reg2 = TEMP_CH1_C_REG; in nct7904_read_temp() 481 reg2 = TEMP_CH1_CH_REG; in nct7904_read_temp() 492 reg2 + channel * 8); in nct7904_read_temp() 569 unsigned int reg1, reg2, reg3; in nct7904_write_temp() local 576 reg2 = TEMP_CH1_W_REG; in nct7904_write_temp() 581 reg2 = TEMP_CH1_WH_REG; in nct7904_write_temp() 586 reg2 = TEMP_CH1_C_REG; in nct7904_write_temp() [all …]
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/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
D | irq_service_dce120.c | 105 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 113 .ack_reg = SRI(reg2, block, reg_num),\ 115 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 117 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
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/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
D | irq_service_dcn303.c | 110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 117 .ack_reg = SRI(reg2, block, reg_num),\ 118 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 119 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
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/drivers/net/ethernet/netronome/nfp/bpf/ |
D | verifier.c | 50 const struct bpf_reg_state *reg2) in nfp_record_adjust_head() argument 59 if (reg2->type != SCALAR_VALUE || !tnum_is_const(reg2->var_off)) in nfp_record_adjust_head() 61 imm = reg2->var_off.value; in nfp_record_adjust_head() 175 const struct bpf_reg_state *reg2 = cur_regs(env) + BPF_REG_2; in nfp_bpf_check_helper_call() local 191 nfp_record_adjust_head(bpf, nfp_prog, meta, reg2); in nfp_bpf_check_helper_call() 204 !nfp_bpf_stack_arg_ok("map_lookup", env, reg2, in nfp_bpf_check_helper_call() 212 !nfp_bpf_stack_arg_ok("map_update", env, reg2, in nfp_bpf_check_helper_call() 222 !nfp_bpf_stack_arg_ok("map_delete", env, reg2, in nfp_bpf_check_helper_call() 305 meta->arg2.reg = *reg2; in nfp_bpf_check_helper_call()
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/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
D | irq_service_dcn10.c | 203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 211 .ack_reg = SRI(reg2, block, reg_num),\ 213 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
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/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
D | irq_service_dcn20.c | 205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument 213 .ack_reg = SRI(reg2, block, reg_num),\ 215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 217 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
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/drivers/gpu/ipu-v3/ |
D | ipu-dc.c | 123 u32 reg1, reg2; in dc_write_tmpl() local 127 reg2 = operand >> 12 | opcode << 1 | stop << 9; in dc_write_tmpl() 130 reg2 = operand >> 17 | opcode << 7 | stop << 9; in dc_write_tmpl() 133 reg2 = operand >> 12 | opcode << 4 | stop << 9; in dc_write_tmpl() 136 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); in dc_write_tmpl()
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/drivers/net/ethernet/mellanox/mlxbf_gige/ |
D | mlxbf_gige_mdio.c | 88 u32 reg1, reg2; in calculate_i1clk() local 92 reg2 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG2); in calculate_i1clk() 98 core_od = (reg2 & MLXBF_GIGE_MDIO_CORE_OD_MASK) >> in calculate_i1clk()
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/drivers/clk/ |
D | clk-axi-clkgen.c | 321 unsigned int reg1, unsigned int reg2, unsigned int reg3, in axi_clkgen_set_div() argument 326 axi_clkgen_mmcm_write(axi_clkgen, reg2, in axi_clkgen_set_div() 407 unsigned int reg1, unsigned int reg2) in axi_clkgen_get_div() argument 412 axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2); in axi_clkgen_get_div()
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/drivers/clk/mvebu/ |
D | armada-37xx-periph.c | 75 void __iomem *reg2; member 151 .reg2 = (void *)_reg2, \ 344 div *= get_div(double_div->reg2, double_div->shift2); in clk_double_div_recalc_rate() 653 rate->reg2 = reg + (u64)rate->reg2; in armada_3700_add_composite_clk()
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/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
D | nv04.c | 204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); in setPLL_double_highregs() local 206 uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0; in setPLL_double_highregs() 266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
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/drivers/iio/light/ |
D | si1145.c | 725 u8 reg1, reg2, shift; in si1145_write_raw() local 736 reg2 = SI1145_PARAM_PS_ADC_COUNTER; in si1145_write_raw() 744 reg2 = SI1145_PARAM_ALSIR_ADC_COUNTER; in si1145_write_raw() 747 reg2 = SI1145_PARAM_ALSVIS_ADC_COUNTER; in si1145_write_raw() 764 ret = si1145_param_set(data, reg2, (~val & 0x07) << 4); in si1145_write_raw()
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/drivers/net/phy/ |
D | adin.c | 186 u16 reg2; member 729 if (stat->reg2 == 0) in adin_read_mmd_stat_regs() 732 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2); in adin_read_mmd_stat_regs()
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