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Searched refs:reg_addr (Results 1 – 25 of 171) sorted by relevance

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/drivers/input/touchscreen/
Dedt-ft5x06.c131 struct edt_reg_addr reg_addr; member
546 struct edt_reg_addr *reg_addr = &tsdata->reg_addr; in edt_ft5x06_restore_reg_parameters() local
548 edt_ft5x06_register_write(tsdata, reg_addr->reg_threshold, in edt_ft5x06_restore_reg_parameters()
550 edt_ft5x06_register_write(tsdata, reg_addr->reg_gain, in edt_ft5x06_restore_reg_parameters()
552 if (reg_addr->reg_offset != NO_REGISTER) in edt_ft5x06_restore_reg_parameters()
553 edt_ft5x06_register_write(tsdata, reg_addr->reg_offset, in edt_ft5x06_restore_reg_parameters()
555 if (reg_addr->reg_offset_x != NO_REGISTER) in edt_ft5x06_restore_reg_parameters()
556 edt_ft5x06_register_write(tsdata, reg_addr->reg_offset_x, in edt_ft5x06_restore_reg_parameters()
558 if (reg_addr->reg_offset_y != NO_REGISTER) in edt_ft5x06_restore_reg_parameters()
559 edt_ft5x06_register_write(tsdata, reg_addr->reg_offset_y, in edt_ft5x06_restore_reg_parameters()
[all …]
/drivers/staging/media/atomisp/pci/css_2401_system/host/
Disys_irq_private.h73 unsigned int reg_addr; in isys_irqc_reg_store() local
78 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_store()
80 "isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); in isys_irqc_reg_store()
82 ia_css_device_store_uint32(reg_addr, value); in isys_irqc_reg_store()
89 unsigned int reg_addr; in isys_irqc_reg_load() local
95 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_load()
96 value = ia_css_device_load_uint32(reg_addr); in isys_irqc_reg_load()
98 "isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); in isys_irqc_reg_load()
/drivers/crypto/cavium/nitrox/
Dnitrox_mbx.c40 u64 reg_addr; in pf2vf_read_mbox() local
42 reg_addr = NPS_PKT_MBOX_VF_PF_PFDATAX(ring); in pf2vf_read_mbox()
43 return nitrox_read_csr(ndev, reg_addr); in pf2vf_read_mbox()
49 u64 reg_addr; in pf2vf_write_mbox() local
51 reg_addr = NPS_PKT_MBOX_PF_VF_PFDATAX(ring); in pf2vf_write_mbox()
52 nitrox_write_csr(ndev, reg_addr, value); in pf2vf_write_mbox()
125 u64 value, reg_addr; in nitrox_pf2vf_mbox_handler() local
130 reg_addr = NPS_PKT_MBOX_INT_LO; in nitrox_pf2vf_mbox_handler()
131 value = nitrox_read_csr(ndev, reg_addr); in nitrox_pf2vf_mbox_handler()
148 nitrox_write_csr(ndev, reg_addr, BIT_ULL(i)); in nitrox_pf2vf_mbox_handler()
[all …]
/drivers/infiniband/hw/qib/
Dqib_diag.c342 const u64 __iomem *reg_addr; in qib_read_umem64() local
347 reg_addr = (const u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); in qib_read_umem64()
348 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { in qib_read_umem64()
354 reg_end = reg_addr + (count / sizeof(u64)); in qib_read_umem64()
357 while (reg_addr < reg_end) { in qib_read_umem64()
358 u64 data = readq(reg_addr); in qib_read_umem64()
364 reg_addr++; in qib_read_umem64()
386 u64 __iomem *reg_addr; in qib_write_umem64() local
391 reg_addr = (u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); in qib_write_umem64()
392 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { in qib_write_umem64()
[all …]
/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
Dgp_device_private.h27 const unsigned int reg_addr, in gp_device_reg_store() argument
32 assert((reg_addr % sizeof(hrt_data)) == 0); in gp_device_reg_store()
33 ia_css_device_store_uint32(GP_DEVICE_BASE[ID] + reg_addr, value); in gp_device_reg_store()
39 const hrt_address reg_addr) in gp_device_reg_load() argument
43 assert((reg_addr % sizeof(hrt_data)) == 0); in gp_device_reg_load()
44 return ia_css_device_load_uint32(GP_DEVICE_BASE[ID] + reg_addr); in gp_device_reg_load()
Dinput_formatter_private.h27 const hrt_address reg_addr, in input_formatter_reg_store() argument
32 assert((reg_addr % sizeof(hrt_data)) == 0); in input_formatter_reg_store()
33 ia_css_device_store_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr, value); in input_formatter_reg_store()
39 const unsigned int reg_addr) in input_formatter_reg_load() argument
43 assert((reg_addr % sizeof(hrt_data)) == 0); in input_formatter_reg_load()
44 return ia_css_device_load_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr); in input_formatter_reg_load()
/drivers/pinctrl/mediatek/
Dpinctrl-mtk-common.c71 unsigned int reg_addr; in mtk_pmx_gpio_set_direction() local
75 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; in mtk_pmx_gpio_set_direction()
79 pctl->devdata->spec_dir_set(&reg_addr, offset); in mtk_pmx_gpio_set_direction()
83 reg_addr = CLR_ADDR(reg_addr, pctl); in mtk_pmx_gpio_set_direction()
85 reg_addr = SET_ADDR(reg_addr, pctl); in mtk_pmx_gpio_set_direction()
87 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); in mtk_pmx_gpio_set_direction()
93 unsigned int reg_addr; in mtk_gpio_set() local
97 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; in mtk_gpio_set()
101 reg_addr = SET_ADDR(reg_addr, pctl); in mtk_gpio_set()
103 reg_addr = CLR_ADDR(reg_addr, pctl); in mtk_gpio_set()
[all …]
/drivers/reset/
Dreset-meson.c40 void __iomem *reg_addr = data->reg_base + (bank << 2); in meson_reset_reset() local
42 writel(BIT(offset), reg_addr); in meson_reset_reset()
54 void __iomem *reg_addr; in meson_reset_level() local
58 reg_addr = data->reg_base + data->param->level_offset + (bank << 2); in meson_reset_level()
62 reg = readl(reg_addr); in meson_reset_level()
64 writel(reg & ~BIT(offset), reg_addr); in meson_reset_level()
66 writel(reg | BIT(offset), reg_addr); in meson_reset_level()
/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_misc.c306 u32 reg_addr; in hns_dsaf_xge_srst_by_port() local
315 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG; in hns_dsaf_xge_srst_by_port()
317 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG; in hns_dsaf_xge_srst_by_port()
319 dsaf_write_sub(dsaf_dev, reg_addr, reg_val); in hns_dsaf_xge_srst_by_port()
343 u32 reg_addr; in hns_dsaf_srst_chns() local
346 reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG; in hns_dsaf_srst_chns()
348 reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG; in hns_dsaf_srst_chns()
350 dsaf_write_sub(dsaf_dev, reg_addr, msk); in hns_dsaf_srst_chns()
461 u32 reg_addr; in hns_ppe_srst_by_port() local
466 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG; in hns_ppe_srst_by_port()
[all …]
/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h46 struct reg_addr { struct
67 static const struct reg_addr page_read_regs_e2[] = { argument
76 static const struct reg_addr page_read_regs_e3[] = {
80 static const struct reg_addr reg_addrs[] = {
1901 static const struct reg_addr idle_reg_addrs[] = {
Dbnx2x_init.h215 u32 reg_addr, reg_bit_map, vnic; in bnx2x_map_q_cos() local
236 reg_addr = BNX2X_VOQ_Q_REG_ADDR(curr_cos, pf_q_num); in bnx2x_map_q_cos()
237 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
238 REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map)); in bnx2x_map_q_cos()
241 reg_addr = BNX2X_VOQ_Q_REG_ADDR(new_cos, pf_q_num); in bnx2x_map_q_cos()
242 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
243 REG_WR(bp, reg_addr, reg_bit_map | q_bit_map); in bnx2x_map_q_cos()
249 reg_addr = BNX2X_Q_CMDQ_REG_ADDR(pf_q_num); in bnx2x_map_q_cos()
250 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
255 REG_WR(bp, reg_addr, reg_bit_map); in bnx2x_map_q_cos()
/drivers/media/pci/cx25821/
Dcx25821-i2c.c82 cx_write(bus->reg_addr, msg->addr << 25); in i2c_sendbytes()
106 cx_write(bus->reg_addr, addr); in i2c_sendbytes()
132 cx_write(bus->reg_addr, addr); in i2c_sendbytes()
173 cx_write(bus->reg_addr, msg->addr << 25); in i2c_readbytes()
198 cx_write(bus->reg_addr, msg->addr << 25); in i2c_readbytes()
344 int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value) in cx25821_i2c_read() argument
365 addr[0] = (reg_addr >> 8); in cx25821_i2c_read()
366 addr[1] = (reg_addr & 0xff); in cx25821_i2c_read()
378 int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value) in cx25821_i2c_write() argument
393 buf[0] = reg_addr >> 8; in cx25821_i2c_write()
[all …]
/drivers/soc/litex/
Dlitex_soc_ctrl.c41 static int litex_check_csr_access(void __iomem *reg_addr) in litex_check_csr_access() argument
45 reg = litex_read32(reg_addr + SCRATCH_REG_OFF); in litex_check_csr_access()
53 litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_TEST_VALUE); in litex_check_csr_access()
54 reg = litex_read32(reg_addr + SCRATCH_REG_OFF); in litex_check_csr_access()
63 litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_VALUE); in litex_check_csr_access()
/drivers/net/ethernet/chelsio/cxgb4vf/
Dadapter.h429 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) in t4_read_reg() argument
431 return readl(adapter->regs + reg_addr); in t4_read_reg()
442 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) in t4_write_reg() argument
444 writel(val, adapter->regs + reg_addr); in t4_write_reg()
467 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr) in t4_read_reg64() argument
469 return readq(adapter->regs + reg_addr); in t4_read_reg64()
480 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, in t4_write_reg64() argument
483 writeq(val, adapter->regs + reg_addr); in t4_write_reg64()
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbtcoutsrc.h691 u8 (*btc_read_1byte)(void *btc_context, u32 reg_addr);
692 void (*btc_write_1byte)(void *btc_context, u32 reg_addr, u32 data);
693 void (*btc_write_1byte_bitmask)(void *btc_context, u32 reg_addr,
695 u16 (*btc_read_2byte)(void *btc_context, u32 reg_addr);
696 void (*btc_write_2byte)(void *btc_context, u32 reg_addr, u16 data);
697 u32 (*btc_read_4byte)(void *btc_context, u32 reg_addr);
698 void (*btc_write_4byte)(void *btc_context, u32 reg_addr, u32 data);
700 void (*btc_write_local_reg_1byte)(void *btc_context, u32 reg_addr,
702 void (*btc_set_bb_reg)(void *btc_context, u32 reg_addr,
704 u32 (*btc_get_bb_reg)(void *btc_context, u32 reg_addr,
[all …]
Dhalbtcoutsrc.c895 static u8 halbtc_read_1byte(void *bt_context, u32 reg_addr) in halbtc_read_1byte() argument
900 return rtl_read_byte(rtlpriv, reg_addr); in halbtc_read_1byte()
903 static u16 halbtc_read_2byte(void *bt_context, u32 reg_addr) in halbtc_read_2byte() argument
908 return rtl_read_word(rtlpriv, reg_addr); in halbtc_read_2byte()
911 static u32 halbtc_read_4byte(void *bt_context, u32 reg_addr) in halbtc_read_4byte() argument
916 return rtl_read_dword(rtlpriv, reg_addr); in halbtc_read_4byte()
919 static void halbtc_write_1byte(void *bt_context, u32 reg_addr, u32 data) in halbtc_write_1byte() argument
924 rtl_write_byte(rtlpriv, reg_addr, data); in halbtc_write_1byte()
927 static void halbtc_bitmask_write_1byte(void *bt_context, u32 reg_addr, in halbtc_bitmask_write_1byte() argument
936 original_value = rtl_read_byte(rtlpriv, reg_addr); in halbtc_bitmask_write_1byte()
[all …]
/drivers/staging/rtl8192u/
Dr819xU_phy.h50 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr,
52 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask);
55 u32 reg_addr, u32 bitmask, u32 data);
58 u32 reg_addr, u32 bitmask);
/drivers/net/ethernet/chelsio/cxgb3/
Dadapter.h270 static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr) in t3_read_reg() argument
272 u32 val = readl(adapter->regs + reg_addr); in t3_read_reg()
274 CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val); in t3_read_reg()
278 static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) in t3_write_reg() argument
280 CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val); in t3_write_reg()
281 writel(val, adapter->regs + reg_addr); in t3_write_reg()
/drivers/media/platform/ti-vpe/
Dvpdma.c587 void vpdma_set_max_size(struct vpdma_data *vpdma, int reg_addr, in vpdma_set_max_size() argument
590 if (reg_addr != VPDMA_MAX_SIZE1 && reg_addr != VPDMA_MAX_SIZE2 && in vpdma_set_max_size()
591 reg_addr != VPDMA_MAX_SIZE3) in vpdma_set_max_size()
592 reg_addr = VPDMA_MAX_SIZE1; in vpdma_set_max_size()
594 write_field_reg(vpdma, reg_addr, width - 1, in vpdma_set_max_size()
597 write_field_reg(vpdma, reg_addr, height - 1, in vpdma_set_max_size()
986 u32 reg_addr = VPDMA_INT_LIST0_MASK + VPDMA_INTX_OFFSET * irq_num; in vpdma_enable_list_complete_irq() local
989 val = read_reg(vpdma, reg_addr); in vpdma_enable_list_complete_irq()
994 write_reg(vpdma, reg_addr, val); in vpdma_enable_list_complete_irq()
1001 u32 reg_addr = VPDMA_INT_LIST0_STAT + VPDMA_INTX_OFFSET * irq_num; in vpdma_get_list_stat() local
[all …]
/drivers/most/
Dmost_usb.c68 u16 reg_addr; member
808 const char *name, u16 *reg_addr) in get_stat_reg_addr() argument
814 *reg_addr = regs[i].reg; in get_stat_reg_addr()
821 #define get_static_reg_addr(regs, name, reg_addr) \ argument
822 get_stat_reg_addr(regs, ARRAY_SIZE(regs), name, reg_addr)
830 u16 reg_addr; in value_show() local
834 return snprintf(buf, PAGE_SIZE, "%04x\n", dci_obj->reg_addr); in value_show()
837 reg_addr = dci_obj->reg_addr; in value_show()
838 else if (get_static_reg_addr(ro_regs, name, &reg_addr) && in value_show()
839 get_static_reg_addr(rw_regs, name, &reg_addr)) in value_show()
[all …]
/drivers/net/ethernet/cavium/thunder/
Dnic_main.c789 u64 reg_addr; in nic_reset_stat_counters() local
793 reg_addr = NIC_PF_VNIC_0_127_RX_STAT_0_13 | in nic_reset_stat_counters()
796 nic_reg_write(nic, reg_addr, 0); in nic_reset_stat_counters()
802 reg_addr = NIC_PF_VNIC_0_127_TX_STAT_0_4 | in nic_reset_stat_counters()
805 nic_reg_write(nic, reg_addr, 0); in nic_reset_stat_counters()
812 reg_addr = (vf << NIC_QS_ID_SHIFT) | in nic_reset_stat_counters()
815 reg_addr |= NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1; in nic_reset_stat_counters()
816 nic_reg_write(nic, reg_addr, 0); in nic_reset_stat_counters()
819 reg_addr |= NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1; in nic_reset_stat_counters()
820 nic_reg_write(nic, reg_addr, 0); in nic_reset_stat_counters()
[all …]
/drivers/crypto/qat/qat_common/
Dqat_hal.c250 unsigned short reg_addr; in qat_hal_get_reg_addr() local
255 reg_addr = 0x80 | (reg_num & 0x7f); in qat_hal_get_reg_addr()
259 reg_addr = reg_num & 0x1f; in qat_hal_get_reg_addr()
264 reg_addr = 0x180 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
267 reg_addr = 0x140 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
272 reg_addr = 0x1c0 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
275 reg_addr = 0x100 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
278 reg_addr = 0x280 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
281 reg_addr = 0x200; in qat_hal_get_reg_addr()
284 reg_addr = 0x220; in qat_hal_get_reg_addr()
[all …]
/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_mdio.c274 u16 hclge_read_phy_reg(struct hclge_dev *hdev, u16 reg_addr) in hclge_read_phy_reg() argument
283 req->reg_addr = cpu_to_le16(reg_addr); in hclge_read_phy_reg()
293 int hclge_write_phy_reg(struct hclge_dev *hdev, u16 reg_addr, u16 val) in hclge_write_phy_reg() argument
302 req->reg_addr = cpu_to_le16(reg_addr); in hclge_write_phy_reg()
/drivers/net/ethernet/atheros/atl1c/
Datl1c_hw.c395 int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data) in atl1c_read_phy_reg() argument
397 return atl1c_read_phy_core(hw, false, 0, reg_addr, phy_data); in atl1c_read_phy_reg()
406 int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data) in atl1c_write_phy_reg() argument
408 return atl1c_write_phy_core(hw, false, 0, reg_addr, phy_data); in atl1c_write_phy_reg()
413 u16 reg_addr, u16 *phy_data) in atl1c_read_phy_ext() argument
415 return atl1c_read_phy_core(hw, true, dev_addr, reg_addr, phy_data); in atl1c_read_phy_ext()
420 u16 reg_addr, u16 phy_data) in atl1c_write_phy_ext() argument
422 return atl1c_write_phy_core(hw, true, dev_addr, reg_addr, phy_data); in atl1c_write_phy_ext()
425 int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data) in atl1c_read_phy_dbg() argument
429 err = atl1c_write_phy_reg(hw, MII_DBG_ADDR, reg_addr); in atl1c_read_phy_dbg()
[all …]
/drivers/input/mouse/
Dsentelic.c71 static int fsp_reg_read(struct psmouse *psmouse, int reg_addr, int *reg_val) in fsp_reg_read() argument
99 if ((addr = fsp_test_invert_cmd(reg_addr)) != reg_addr) { in fsp_reg_read()
101 } else if ((addr = fsp_test_swap_cmd(reg_addr)) != reg_addr) { in fsp_reg_read()
124 reg_addr, *reg_val, rc); in fsp_reg_read()
128 static int fsp_reg_write(struct psmouse *psmouse, int reg_addr, int reg_val) in fsp_reg_write() argument
139 if ((v = fsp_test_invert_cmd(reg_addr)) != reg_addr) { in fsp_reg_write()
143 if ((v = fsp_test_swap_cmd(reg_addr)) != reg_addr) { in fsp_reg_write()
176 reg_addr, reg_val, rc); in fsp_reg_write()

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