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Searched refs:reg_idx (Results 1 – 25 of 77) sorted by relevance

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/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_interrupts.c132 int reg_idx; in dpu_hw_intr_clear_intr_status_nolock() local
137 reg_idx = DPU_IRQ_REG(irq_idx); in dpu_hw_intr_clear_intr_status_nolock()
138 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_clear_intr_status_nolock()
148 int reg_idx; in dpu_hw_intr_dispatch_irq() local
164 for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { in dpu_hw_intr_dispatch_irq()
165 if (!test_bit(reg_idx, &intr->irq_mask)) in dpu_hw_intr_dispatch_irq()
169 irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off); in dpu_hw_intr_dispatch_irq()
172 enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off); in dpu_hw_intr_dispatch_irq()
176 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_hw_intr_dispatch_irq()
189 irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1); in dpu_hw_intr_dispatch_irq()
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Ddpu_hw_interrupts.h34 #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) argument
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_lib.c24 u16 reg_idx, pool; in ixgbe_cache_ring_dcb_sriov() local
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
37 for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
41 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
43 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
47 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
48 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
51 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
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Dixgbe_main.c1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1315 u8 reg_idx = rx_ring->reg_idx; in ixgbe_update_rx_dca() local
1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); in ixgbe_update_rx_dca()
2472 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbe_configure_msix()
2475 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbe_configure_msix()
3468 u8 reg_idx = ring->reg_idx; in ixgbe_configure_tx_ring() local
3475 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); in ixgbe_configure_tx_ring()
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/drivers/staging/media/atomisp/pci/css_2401_system/host/
Disys_irq_private.h70 const unsigned int reg_idx, in isys_irqc_reg_store() argument
76 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); in isys_irqc_reg_store()
78 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_store()
87 const unsigned int reg_idx) in isys_irqc_reg_load() argument
93 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); in isys_irqc_reg_load()
95 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_load()
Disys_stream2mmio_private.h139 const uint32_t reg_idx) in stream2mmio_reg_load() argument
147 (reg_bank_offset + reg_idx) * sizeof(hrt_data)); in stream2mmio_reg_load()
/drivers/i2c/
Di2c-slave-testunit.c41 u8 reg_idx; member
92 bool is_proc_call = tu->reg_idx == 3 && tu->regs[TU_REG_DATAL] == 1 && in i2c_slave_testunit_slave_cb()
101 if (tu->reg_idx < TU_NUM_REGS) in i2c_slave_testunit_slave_cb()
102 tu->regs[tu->reg_idx] = *val; in i2c_slave_testunit_slave_cb()
106 if (tu->reg_idx <= TU_NUM_REGS) in i2c_slave_testunit_slave_cb()
107 tu->reg_idx++; in i2c_slave_testunit_slave_cb()
116 if (tu->reg_idx == TU_NUM_REGS) { in i2c_slave_testunit_slave_cb()
125 tu->reg_idx = 0; in i2c_slave_testunit_slave_cb()
/drivers/soc/renesas/
Dr8a779a0-sysc.c170 static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask) in clear_irq_flags() argument
175 iowrite32(isr_mask, r8a779a0_sysc_base + SYSCISCR(reg_idx)); in clear_irq_flags()
177 ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx), in clear_irq_flags()
191 unsigned int reg_idx, bit_idx; in r8a779a0_sysc_power() local
200 reg_idx = pdr / NUM_DOMAINS_EACH_REG; in r8a779a0_sysc_power()
209 iowrite32(ioread32(r8a779a0_sysc_base + SYSCIER(reg_idx)) | isr_mask, in r8a779a0_sysc_power()
210 r8a779a0_sysc_base + SYSCIER(reg_idx)); in r8a779a0_sysc_power()
211 iowrite32(ioread32(r8a779a0_sysc_base + SYSCIMR(reg_idx)) | isr_mask, in r8a779a0_sysc_power()
212 r8a779a0_sysc_base + SYSCIMR(reg_idx)); in r8a779a0_sysc_power()
214 ret = clear_irq_flags(reg_idx, isr_mask); in r8a779a0_sysc_power()
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/drivers/irqchip/
Dirq-mvebu-sei.c59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq() local
62 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq() local
73 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
75 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
82 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq() local
87 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
89 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
354 u32 reg_idx; in mvebu_sei_reset() local
357 for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++) { in mvebu_sei_reset()
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Dirq-pruss-intc.c181 u8 ch, host, reg_idx; in pruss_intc_map() local
193 reg_idx = hwirq / 32; in pruss_intc_map()
197 pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val); in pruss_intc_map()
198 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); in pruss_intc_map()
224 u8 ch, host, reg_idx; in pruss_intc_unmap() local
241 reg_idx = hwirq / 32; in pruss_intc_unmap()
245 pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val); in pruss_intc_unmap()
247 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); in pruss_intc_unmap()
/drivers/misc/habanalabs/goya/
Dgoya_coresight.c236 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in goya_config_stm()
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()
309 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { in goya_config_etf()
314 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in goya_config_etf()
484 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { in goya_config_funnel()
489 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in goya_config_funnel()
505 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { in goya_config_bmon()
510 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in goya_config_bmon()
534 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD && in goya_config_bmon()
535 params->reg_idx != GOYA_BMON_PCIE_MSTR_WR && in goya_config_bmon()
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/drivers/sh/intc/
Dhandle.c41 unsigned int *reg_idx, in _intc_mask_data() argument
48 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { in _intc_mask_data()
49 mr = desc->hw.mask_regs + *reg_idx; in _intc_mask_data()
82 (*reg_idx)++; in _intc_mask_data()
109 unsigned int *reg_idx, in _intc_prio_data() argument
116 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { in _intc_prio_data()
117 pr = desc->hw.prio_regs + *reg_idx; in _intc_prio_data()
151 (*reg_idx)++; in _intc_prio_data()
/drivers/net/ethernet/intel/fm10k/
Dfm10k_pci.c876 u8 reg_idx = ring->reg_idx; in fm10k_configure_tx_ring() local
879 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0); in fm10k_configure_tx_ring()
885 fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in fm10k_configure_tx_ring()
886 fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32); in fm10k_configure_tx_ring()
887 fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size); in fm10k_configure_tx_ring()
890 fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0); in fm10k_configure_tx_ring()
891 fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0); in fm10k_configure_tx_ring()
894 ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)]; in fm10k_configure_tx_ring()
906 fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint); in fm10k_configure_tx_ring()
909 fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx), in fm10k_configure_tx_ring()
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/drivers/media/platform/mtk-vcodec/
Dmtk_vcodec_util.c24 unsigned int reg_idx) in mtk_vcodec_get_reg_addr() argument
28 if (!data || reg_idx >= NUM_MAX_VCODEC_REG_BASE) { in mtk_vcodec_get_reg_addr()
29 mtk_v4l2_err("Invalid arguments, reg_idx=%d", reg_idx); in mtk_vcodec_get_reg_addr()
32 return ctx->dev->reg_base[reg_idx]; in mtk_vcodec_get_reg_addr()
/drivers/net/ethernet/intel/ixgbevf/
Dixgbevf_main.c200 u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx)); in ixgbevf_get_tx_pending()
201 u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx)); in ixgbevf_get_tx_pending()
385 IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
386 IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
1365 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1368 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1691 u8 reg_idx = ring->reg_idx; in ixgbevf_configure_tx_ring() local
1694 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); in ixgbevf_configure_tx_ring()
1697 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in ixgbevf_configure_tx_ring()
1698 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32); in ixgbevf_configure_tx_ring()
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/drivers/bus/
Dimx-weim.c136 int reg_idx, num_regs; in weim_timing_setup() local
158 for (reg_idx = 0; reg_idx < num_regs; reg_idx++) { in weim_timing_setup()
161 reg_idx * OF_REG_SIZE, &cs_idx); in weim_timing_setup()
/drivers/misc/habanalabs/gaudi/
Dgaudi_coresight.c397 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in gaudi_config_stm()
402 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in gaudi_config_stm()
475 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { in gaudi_config_etf()
480 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in gaudi_config_etf()
690 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { in gaudi_config_funnel()
695 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in gaudi_config_funnel()
710 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { in gaudi_config_bmon()
715 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in gaudi_config_bmon()
778 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) { in gaudi_config_spmu()
783 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE; in gaudi_config_spmu()
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/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
Disys_irq_public.h31 const unsigned int reg_idx,
35 const unsigned int reg_idx);
/drivers/net/ethernet/intel/ice/
Dice_xsk.c84 reg = rx_ring->reg_idx; in ice_qvec_dis_irq()
92 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), 0); in ice_qvec_dis_irq()
106 u16 reg_idx = q_vector->reg_idx; in ice_qvec_cfg_msix() local
114 ice_cfg_txq_interrupt(vsi, ring->reg_idx, reg_idx, in ice_qvec_cfg_msix()
118 ice_cfg_rxq_interrupt(vsi, ring->reg_idx, reg_idx, in ice_qvec_cfg_msix()
/drivers/hwtracing/coresight/
Dcoresight-cti-sysfs.c839 int used = 0, reg_idx; in chan_xtrigs_in_show() local
843 for (reg_idx = 0; reg_idx < nr_trig_max; reg_idx++) { in chan_xtrigs_in_show()
844 if (chan_mask & cfg->ctiinen[reg_idx]) in chan_xtrigs_in_show()
845 used += sprintf(buf + used, "%d ", reg_idx); in chan_xtrigs_in_show()
859 int used = 0, reg_idx; in chan_xtrigs_out_show() local
863 for (reg_idx = 0; reg_idx < nr_trig_max; reg_idx++) { in chan_xtrigs_out_show()
864 if (chan_mask & cfg->ctiouten[reg_idx]) in chan_xtrigs_out_show()
865 used += sprintf(buf + used, "%d ", reg_idx); in chan_xtrigs_out_show()
/drivers/regulator/
Dda9121-regulator.c574 int reg_idx = item->reg_index; in da9121_status_poll_on() local
577 bool persisting = (chip->persistent[reg_idx] & item->event_bit); in da9121_status_poll_on()
578 bool now_cleared = !(status[reg_idx] & item->status_bit); in da9121_status_poll_on()
581 clear[reg_idx] |= item->mask_bit; in da9121_status_poll_on()
582 chip->persistent[reg_idx] &= ~item->event_bit; in da9121_status_poll_on()
645 int reg_idx = item->reg_index; in da9121_irq_handler() local
647 bool enabled = !(mask[reg_idx] & item->mask_bit); in da9121_irq_handler()
648 bool active = (event[reg_idx] & item->event_bit); in da9121_irq_handler()
653 chip->persistent[reg_idx] |= item->event_bit; in da9121_irq_handler()
657 handled[reg_idx] |= item->event_bit; in da9121_irq_handler()
/drivers/perf/hisilicon/
Dhisi_uncore_l3c_pmu.c109 u32 reg, reg_idx, shift, val; in hisi_l3c_pmu_write_ds() local
120 reg_idx = idx % 4; in hisi_l3c_pmu_write_ds()
121 shift = 8 * reg_idx; in hisi_l3c_pmu_write_ds()
248 u32 reg, reg_idx, shift, val; in hisi_l3c_pmu_write_evtype() local
258 reg_idx = idx % 4; in hisi_l3c_pmu_write_evtype()
259 shift = 8 * reg_idx; in hisi_l3c_pmu_write_evtype()
/drivers/net/ethernet/intel/i40e/
Di40e_virtchnl_pf.c377 u32 reg, reg_idx; in i40e_config_irq_link_list() local
383 reg_idx = I40E_VPINT_LNKLST0(vf->vf_id); in i40e_config_irq_link_list()
385 reg_idx = I40E_VPINT_LNKLSTN( in i40e_config_irq_link_list()
391 wr32(hw, reg_idx, I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK); in i40e_config_irq_link_list()
416 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
421 reg_idx = I40E_QINT_RQCTL(pf_queue_id); in i40e_config_irq_link_list()
425 reg_idx = I40E_QINT_TQCTL(pf_queue_id); in i40e_config_irq_link_list()
450 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
489 u32 v_idx, reg_idx, reg; in i40e_release_iwarp_qvlist() local
499 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx; in i40e_release_iwarp_qvlist()
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Di40e_client.c149 u32 reg_idx; in i40e_client_release_qvlist() local
154 reg_idx = I40E_PFINT_LNKLSTN(qv_info->v_idx - 1); in i40e_client_release_qvlist()
155 wr32(&pf->hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_release_qvlist()
570 u32 v_idx, i, reg_idx, reg; in i40e_client_setup_qvlist() local
590 reg_idx = I40E_PFINT_LNKLSTN(v_idx - 1); in i40e_client_setup_qvlist()
594 wr32(hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_setup_qvlist()
600 wr32(hw, reg_idx, reg); in i40e_client_setup_qvlist()
/drivers/hwmon/
Dw83791d.c767 u8 reg_idx = 0; in store_pwmenable() local
780 reg_idx = 0; in store_pwmenable()
785 reg_idx = 0; in store_pwmenable()
790 reg_idx = 1; in store_pwmenable()
796 reg_cfg_tmp = w83791d_read(client, W83791D_REG_FAN_CFG[reg_idx]); in store_pwmenable()
800 w83791d_write(client, W83791D_REG_FAN_CFG[reg_idx], reg_cfg_tmp); in store_pwmenable()
874 u8 reg_idx = 0; in store_temp_tolerance() local
883 reg_idx = 0; in store_temp_tolerance()
888 reg_idx = 0; in store_temp_tolerance()
893 reg_idx = 1; in store_temp_tolerance()
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